research-article

Computational RAM: Implementing Processors in Memory

Authors:

Robert McKenzieAuthors Info & Claims

IEEE Design & Test, Volume 16, Issue 1

Pages 32 - 41

https://doi.org/10.1109/54.748803

Published: 01 January 1999 Publication History

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Abstract

Computational RAM (C·RAM) is an integrated circuit that implements a "smart memory" whereby processing elements are integrated into the memory chip. C·RAM can function either as a conventional memory chip or as a SIMD computer. When used as a memory, C·RAM is competitive with conventional DRAM in terms of access time, packaging and cost. In fact, adding processing elements to DRAM adds only 3-20% in area and 10-25% in power consumption. When used as a SIMD computer, C·RAM can run suitable parallel applications thousands of times faster than a CPU. We argue that the key to successfully integrating processing power to memory is to use an architecture that preserves and exploits the features and characteristics of memory. If effective use is to be made of the internal memory bandwidth, then adding logic to memory is not simply a question of bolting together two existing designs.

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Arora ABhamburkar ABorda AAnand TSehgal RHanindhito BGaillardon PKulkarni JJohn L(2023)CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning AccelerationACM Transactions on Reconfigurable Technology and Systems10.1145/360350416:3(1-34)Online publication date: 27-Jul-2023
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1. Hardware
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Published In

IEEE Design & Test Volume 16, Issue 1

January 1999

84 pages

ISSN:0740-7475

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 January 1999

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Arora ABhamburkar ABorda AAnand TSehgal RHanindhito BGaillardon PKulkarni JJohn L(2023)CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning AccelerationACM Transactions on Reconfigurable Technology and Systems10.1145/360350416:3(1-34)Online publication date: 27-Jul-2023
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Devic ARai SSivasubramaniam AAkel AEilert SEno JSalapura VZahran MChong FTang L(2022)To PIM or not for emerging general purpose processing in DDR memory systemsProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527431(231-244)Online publication date: 18-Jun-2022
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