More Web Proxy on the site http://driver.im/

research-article

MOCA: an Inter/Intra-Chip Optical Network for Memory

Authors:

Rafael K. V. Maeda,

Luan H.K. Duong,

Zhe WangAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 86, Pages 1 - 6

https://doi.org/10.1145/3061639.3062286

Published: 18 June 2017 Publication History

Abstract

The memory wall problem is due to the imbalanced developments and separation of processors and memories. It is becoming acute as more and more processor cores are integrated into a single chip and demand higher memory bandwidth through limited chip pins. Optical memory interconnection network (OMIN) promises high bandwidth, bandwidth density, and energy efficiency, and can potentially alleviate the memory wall problem. In this paper, we propose an optical inter/intra-chip processor-memory communication architecture, called MOCA. Experimental results and analysis show that MOCA can significantly improve system performance and energy efficiency. For example, comparing to Hybrid Memory Cube (HMC), MOCA can speedup application execution time by 2.6x, reduce communication latency by 75%, and improve energy efficiency by 3.4x for 256-core processors in 7 nm technology.

References

[1]

A. N. Udipi et al., "Combining Memory and a Controller with Photonics Through 3D-stacking to Enable Scalable and Energy-efficient Systems," in ISCA, 2011.

Digital Library

[2]

A. Hadke et al., "Design and Evaluation of an Optical CPU-DRAM Interconnect," in ICCD, 2008.

[3]

S. Beamer et al., "Re-architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics," in ISCA, 2010.

Digital Library

[4]

C. Batten et al., "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics," in HOTI, 2008.

Digital Library

[5]

D. Brunina et al., "An Energy-Efficient Optically Connected Memory Module for Hybrid Packet- and Circuit-Switched Optical Networks," JSTQE, vol. 19, March 2013.

[6]

S. L. Beux et al., "Potential and Pitfalls of Silicon Photonics Computing and Interconnect," in ISCAS, 2013.

[7]

W. Y. Tsai et al., "A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link," TCSI, vol. 59, pp. 2600--2610, Nov 2012.

[8]

G. Kim et al., "Memory-centric System Interconnect Design with Hybrid Memory Cubes," in PACT, 2013.

Digital Library

[9]

T. Krishna et al., "Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip," in MICRO, 2014.

[10]

"Hybrid Memory Cube Specification 2.0," Technical Publication, 2014.

[11]

J. Zhan et al., "A Unified Memory Network Architecture for In-Memory Computing in Commodity Servers," in MICRO, 2016.

[12]

S. Li et al., "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," in MICRO, 2009.

Digital Library

[13]

X. Wu et al., "An Inter/Intra-Chip Optical Network for Manycore Processors," TVLSI, vol. 23, pp. 678--691, April 2015.

[14]

C. Schow et al., "A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single "Holey" CMOS IC," JLT, vol. 29, pp. 542--553, Feb 2011.

[15]

R. K. V. Maeda et al., "JADE: A Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models," in AISTECS, 2016.

Digital Library

[16]

J. D. McCalpin, "Memory Bandwidth and Machine Balance in Current High Performance Computers," TCCA, pp. 19--25, Dec. 1995.

[17]

P. Rosenfeld et al., "DRAMSim2: A Cycle Accurate Memory System Simulator," CAL, vol. 10, pp. 16--19, Jan 2011.

Digital Library

[18]

O. Naji et al., "A High-level DRAM Timing, Power and Area Exploration Tool," in SAMOS, 2015.

[19]

O. Naji et al., "Calculating Memory System Power for DDR3," Technical Publication, 2014.

[20]

Z. Wang et al., "Improve Chip Pin Performance Using Optical Interconnects," TVLSI, vol. 24, pp. 1574--1587, April 2016.

[21]

"Corning® Single-Mode Optical Fiber," Technical Publication.

[22]

Q. Xu et al., "Micrometre-scale Silicon Electro-optic Modulator," Nature, vol. 435, no. 7040, pp. 325--327, 2005.

[23]

Y. Zhang et al., "Towards Adaptively Tuned Silicon Microring Resonators for Optical Networks-on-Chip Applications," JSTQE, vol. 20, pp. 136--149, July 2014.

[24]

A. Supalov et al., Optimizing HPC Applications with Intel Cluster Tools. Apress, 2014.

Digital Library

Cited By

Nedbailo YPetrov I(2020)Increasing DDR4 SDRAM throughput in parallel workloads2020 Moscow Workshop on Electronic and Networking Technologies (MWENT)10.1109/MWENT47943.2020.9067412(1-4)Online publication date: Mar-2020
https://doi.org/10.1109/MWENT47943.2020.9067412
Werner SFotouhi PXiao XFariborz MYoo SMichelogiannakis GVasudevan D(2019)3D photonics as enabling technology for deep 3D DRAM stackingProceedings of the International Symposium on Memory Systems10.1145/3357526.3357559(206-221)Online publication date: 30-Sep-2019
https://dl.acm.org/doi/10.1145/3357526.3357559
Nedbailo Y(2019)Avoiding common scalability pitfalls in shared-cache chip multiprocessor design2019 International Conference on Engineering and Telecommunication (EnT)10.1109/EnT47717.2019.9030579(1-5)Online publication date: Nov-2019
https://doi.org/10.1109/EnT47717.2019.9030579
Show More Cited By

Recommendations

MoCA: A Middleware for Developing Collaborative Applications for Mobile Users

The Mobile Collaboration Architecture is a middleware architecture for developing and deploying context-aware collaborative applications for mobile users. MoCA comprises client and server APIs, a set of core services for registering applications, the ...
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. ...
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 June 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article
Research
Refereed limited

Conference

DAC '17

Sponsor:

EDAC
SIGDA

DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
217
Total Downloads

Downloads (Last 12 months)7
Downloads (Last 6 weeks)0

Reflects downloads up to 11 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Nedbailo YPetrov I(2020)Increasing DDR4 SDRAM throughput in parallel workloads2020 Moscow Workshop on Electronic and Networking Technologies (MWENT)10.1109/MWENT47943.2020.9067412(1-4)Online publication date: Mar-2020
https://doi.org/10.1109/MWENT47943.2020.9067412
Werner SFotouhi PXiao XFariborz MYoo SMichelogiannakis GVasudevan D(2019)3D photonics as enabling technology for deep 3D DRAM stackingProceedings of the International Symposium on Memory Systems10.1145/3357526.3357559(206-221)Online publication date: 30-Sep-2019
https://dl.acm.org/doi/10.1145/3357526.3357559
Nedbailo Y(2019)Avoiding common scalability pitfalls in shared-cache chip multiprocessor design2019 International Conference on Engineering and Telecommunication (EnT)10.1109/EnT47717.2019.9030579(1-5)Online publication date: Nov-2019
https://doi.org/10.1109/EnT47717.2019.9030579
Liou YLin HShen TCai SWu YLiao YLin HChen TLin TChen Y(2019)Integration of Nanoscale and Macroscale Graphene Heterostructures for Flexible and Multilevel Nonvolatile Photoelectronic MemoryACS Applied Nano Materials10.1021/acsanm.9b021493:1(608-616)Online publication date: 27-Dec-2019
https://doi.org/10.1021/acsanm.9b02149
Vivas Maeda RYang PLi HTian ZWang ZWang ZChen XFeng JXu J(2019)A Fast Joint Application-Architecture Exploration Platform for Heterogeneous SystemsEmbedded, Cyber-Physical, and IoT Systems10.1007/978-3-030-16949-7_9(203-232)Online publication date: 29-Jun-2019
https://doi.org/10.1007/978-3-030-16949-7_9
Werner SFotouhi PProietti RXiao XYoo SLu ZVangal SXu JBogdan P(2018)Towards energy-efficient high-throughput photonic NoCs for 2.5D integrated systemsProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306624(1-8)Online publication date: 4-Oct-2018
https://dl.acm.org/doi/10.5555/3306619.3306624
Li MTseng TBertozzi DTala MSchlichtmann U(2018)CustomTopo: A Topology Generation Method for Application-Specific Wavelength-Routed Optical NoCs2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3240789(1-8)Online publication date: 5-Nov-2018
https://dl.acm.org/doi/10.1145/3240765.3240789
Werner SFotouhi PProietti RYoo SJacob B(2018)AWGR-based optical processor-to-memory communication for low-latency, low-energy vault accessesProceedings of the International Symposium on Memory Systems10.1145/3240302.3240318(269-278)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240318
Werner SFotouhi PProietti RXiao XYoo S(2018)Towards Energy-Efficient High-Throughput Photonic NoCs for 2.5D Integrated Systems: A Case for AWGRs2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)10.1109/NOCS.2018.8512157(1-8)Online publication date: Oct-2018
https://doi.org/10.1109/NOCS.2018.8512157
Van Winkle SKodi ABunescu RLouri A(2018)Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00048(480-491)Online publication date: Feb-2018
https://doi.org/10.1109/HPCA.2018.00048

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents