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Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Authors:

Christopher Batten,

Vladimir Stojanović,

Krste AsanovićAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 38, Issue 3

Pages 129 - 140

https://doi.org/10.1145/1816038.1815978

Published: 19 June 2010 Publication History

Abstract

The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM architectures appears unlikely to suffice, being constrained by processor and DRAM pin-bandwidth density and by total DRAM chip power, including off-chip signaling, cross-chip interconnect, and bank access energy. In this work, we redesign the DRAM main memory system using a proposed monolithically integrated silicon photonics technology and show that our photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues. Photonics can provide high aggregate pin-bandwidth density through dense wavelength-division multiplexing. Photonic signaling provides energy-efficient communication, which we exploit to not only reduce chip-to-chip interconnect power but to also reduce cross-chip interconnect power by extending the photonic links deep into the actual PIDRAM chips. To complement these large improvements in interconnect bandwidth and power, we decrease the number of bits activated per bank to improve the energy efficiency of the PIDRAM banks themselves. Our most promising design point yields approximately a 10x power reduction for a single-chip PIDRAM channel with similar throughput and area as a projected future electrical-only DRAM. Finally, we propose optical power guiding as a new technique that allows a single PIDRAM chip design to be used efficiently in several multi-chip configurations that provide either increased aggregate capacity or bandwidth.

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Cited By

Demirer FBaron YReniers SPustakhod DLavrijsen Rvan der Tol JKoopmans B(2022)An integrated photonic device for on-chip magneto-optical memory readingNanophotonics10.1515/nanoph-2022-016511:14(3319-3329)Online publication date: 15-Jun-2022
https://doi.org/10.1515/nanoph-2022-0165
Ma YJoardar BPande PJoshi A(2022)Interconnect and Integration TechnologyEmerging Computing: From Devices to Systems10.1007/978-981-16-7487-7_4(85-105)Online publication date: 9-Jul-2022
https://doi.org/10.1007/978-981-16-7487-7_4
Fariborz MSamani MFotouhi PProietti RYi IAkella VLowe-Power JPalermo SYoo S(2022)LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular WorkloadsHigh Performance Computing10.1007/978-3-031-07312-0_3(44-64)Online publication date: 29-May-2022
https://dl.acm.org/doi/10.1007/978-3-031-07312-0_3
Show More Cited By

Index Terms

Re-architecting DRAM memory systems with monolithically integrated silicon photonics
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Integrated circuits
    1. Interconnect
      1. Metallic interconnect
      2. Photonic and optical interconnect
    2. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 38, Issue 3

ISCA '10

June 2010

508 pages

ISSN:0163-5964

DOI:10.1145/1816038

Issue’s Table of Contents

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture
June 2010
520 pages
ISBN:9781450300537
DOI:10.1145/1815961
General Chair:
André Seznec
INRIA Rennes
,
Program Chairs:
Uri Weiser
Technion
,
Ronny Ronen
Intel

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 June 2010

Published in SIGARCH Volume 38, Issue 3

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Cited By

Demirer FBaron YReniers SPustakhod DLavrijsen Rvan der Tol JKoopmans B(2022)An integrated photonic device for on-chip magneto-optical memory readingNanophotonics10.1515/nanoph-2022-016511:14(3319-3329)Online publication date: 15-Jun-2022
https://doi.org/10.1515/nanoph-2022-0165
Ma YJoardar BPande PJoshi A(2022)Interconnect and Integration TechnologyEmerging Computing: From Devices to Systems10.1007/978-981-16-7487-7_4(85-105)Online publication date: 9-Jul-2022
https://doi.org/10.1007/978-981-16-7487-7_4
Fariborz MSamani MFotouhi PProietti RYi IAkella VLowe-Power JPalermo SYoo S(2022)LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular WorkloadsHigh Performance Computing10.1007/978-3-031-07312-0_3(44-64)Online publication date: 29-May-2022
https://dl.acm.org/doi/10.1007/978-3-031-07312-0_3
Kim MKim YHan T(2020)System-Level Signal Analysis Methodology for Optical Network-on-Chip Using Linear Model-Based CharacterizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294570939:10(2761-2771)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2945709
Hazarika APoddar SRahaman H(2020)Survey on memory management techniques in heterogeneous computing systemsIET Computers & Digital Techniques10.1049/iet-cdt.2019.009214:2(47-60)Online publication date: 21-Jan-2020
https://doi.org/10.1049/iet-cdt.2019.0092
Werner SFotouhi PXiao XFariborz MYoo SMichelogiannakis GVasudevan D(2019)3D photonics as enabling technology for deep 3D DRAM stackingProceedings of the International Symposium on Memory Systems10.1145/3357526.3357559(206-221)Online publication date: 30-Sep-2019
https://dl.acm.org/doi/10.1145/3357526.3357559
Yang WChen JZhang YZhang YHe JFang X(2019)Silicon‐Compatible Photodetectors: Trends to Monolithically Integrate Photosensors with Chip TechnologyAdvanced Functional Materials10.1002/adfm.20180818229:18(1808182)Online publication date: 25-Feb-2019
https://doi.org/10.1002/adfm.201808182
Werner SFotouhi PProietti RYoo SJacob B(2018)AWGR-based optical processor-to-memory communication for low-latency, low-energy vault accessesProceedings of the International Symposium on Memory Systems10.1145/3240302.3240318(269-278)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240318
Kodi AShifflet KKaya SLaha SLouri A(2018)Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architectures2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2018.00110(1010-1019)Online publication date: May-2018
https://doi.org/10.1109/IPDPS.2018.00110
Van Winkle SKodi ABunescu RLouri A(2018)Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00048(480-491)Online publication date: Feb-2018
https://doi.org/10.1109/HPCA.2018.00048
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