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Classifying load and store instructions for memory renaming

Published: 01 May 1999 Publication History
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  • (2022)NvMRProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527413(1-13)Online publication date: 18-Jun-2022
  • (2015)Design optimization of sense amplifiers using deeply-scaled FinFET devicesSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085439(280-283)Online publication date: Mar-2015
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cover image ACM Conferences
ICS '99: Proceedings of the 13th international conference on Supercomputing
June 1999
509 pages
ISBN:158113164X
DOI:10.1145/305138
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 May 1999

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Cited By

View all
  • (2024)Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00017(88-102)Online publication date: 29-Jun-2024
  • (2022)NvMRProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527413(1-13)Online publication date: 18-Jun-2022
  • (2015)Design optimization of sense amplifiers using deeply-scaled FinFET devicesSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085439(280-283)Online publication date: Mar-2015
  • (2009)Synchronization optimizations for efficient execution on multi-coresProceedings of the 23rd international conference on Supercomputing10.1145/1542275.1542303(169-180)Online publication date: 8-Jun-2009
  • (2006)Feedback-directed memory disambiguation through store distance analysisProceedings of the 20th annual international conference on Supercomputing10.1145/1183401.1183440(278-287)Online publication date: 28-Jun-2006
  • (2004)Dynamic memory instruction bypassingInternational Journal of Parallel Programming10.1023/B:IJPP.0000029273.49634.1932:3(199-224)Online publication date: 1-Jun-2004
  • (2002)Cost-Effective Compiler Directed Memory Prefetching and BypassingProceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques10.5555/645989.674313(189-198)Online publication date: 22-Sep-2002
  • (2002)Cost-effective compiler directed memory prefetching and bypassingProceedings.International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2002.1106017(189-198)Online publication date: 2002
  • (2001)A novel renaming mechanism that boosts software prefetchingProceedings of the 15th international conference on Supercomputing10.1145/377792.377907(501-510)Online publication date: 17-Jun-2001
  • (2000)Understanding the backward slices of performance degrading instructionsACM SIGARCH Computer Architecture News10.1145/342001.33967628:2(172-181)Online publication date: 1-May-2000
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