[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/305138.305189acmconferencesArticle/Chapter ViewAbstractPublication PagesicsConference Proceedingsconference-collections
Article
Free access

Reducing cache misses using hardware and software page placement

Published: 01 May 1999 Publication History
First page of PDF

References

[1]
A. Agarwal and S. D. Pudar. Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. Proceedings of the 20th Annual International ~mposium on Computer Architecture, 21(2):179-190, May 1993.
[2]
B. Bershad, D. Lee, T. Romer, and J.B. Chert. Avoiding conflict misses dynamically in large direct-mapped caches. In Proceedings oft he 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 158-170, October 1994.
[3]
E. Bugnion, J. Anderson, T. Mowry, M. RosenBlum, and M. Lam. Compiler-directed page coloring for multiprocessors. In Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.
[4]
D.C. Burger and T.M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
[5]
B. Calder, D, Gnmwald, and J. Emer. Predictive sequential associative cache. In Proceedings of the Second International Symposium on High-Performance Computer Architecture, February 1996.
[6]
B. Calder, C. Krintz, S. John, and T. Austin. Cache-conscious data placement. In 8th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.
[7]
S. Carr, K. S. McKinley, and C.-W. Tseng. Compiler opfimizations for improving data locality. Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, 28(5):252-262, October 1994.
[8]
J. Carter, W. Hsieh, L. Stoller, M. Swanson, L. Zhang, E. Brunwand, A. Davis, C. Kuo, R. Kuramkote, M. Parker, L, Schaelicke, and T. Tateyama. Impulse: Building a smarter memory controller. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, January 1999.
[9]
T.M. Come, K.N. Menezos, P.M. Mills, and B.A. Patel. Optimization of instruction fetch mechanisms for high issue rates. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 333-344, June 1995.
[10]
D. Eng/er, M. Kaashoek, and J. O'Toole Jr. Exokemel: An operating system architecture for application-level resource management. In Proceedings of the Fifteenth Symposium on Operating Systems Principles, December 1995.
[11]
K. Ghose and M.B. Kamble. Energy eft%lent cache organizations for superscalar processors. In Power-Driven Microarchitecture Workshop, June 1998.
[12]
N. Gloy, T. Blockwell, M.D. Smith, and B. Calder. Procedure placement using temporal ordering information. In 30th International Symposium on Microarchiteeture, December 1997.
[13]
L. Hammond, B. Nayfeh, and K. Olukotun. A single-chip mulfiproessor. IEE~ Computer, Special Issue on Billion-Transistor Processors, September 1997.
[14]
K. Harry and D.R. Cheriton. Application-controlled physical memory using external page cache management. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V), October 1992.
[15]
A.H. Hashemi, D.R. Kaeli, and B. Calder. Efficient procedure mapping using cache lince coloring. In Proceedings of the SIGPLAN '97 Conjbrence on Programming Language Design and Implementation, pages 171-182, June 1997.
[16]
W.W. Hwu and P.P. Chang. Achieving high instruction cache performance with an optimizing compiler. In 16th Annual International Symposium on Computer Architecture, pages 242-251. ACM, 1989.
[17]
B. Jacob and T. Mudge. A look at several memory management units, fib-refill mechanisms,and page table organizations. In Eigth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.
[18]
T. johnson, M. Merten, and W. Hwu. Run-time spatial locality detection and optimization. In 30th International Symposium on Microarchitecture, December 1997.
[19]
N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 364-373, May 1990.
[20]
M.B. Kamble and K. Ghose. Analytical energy dissipation models for low-power caches. In Proceedings of the 1997 International Symposium on Low Power Electronics and Design, pages 143-148, 1997.
[21]
R. Kessler and M. Hill. Page placement algorithms for large realindexed caches. Transactions on Computer Systems, 10(4), November 1992.
[22]
R. E. Kessler. Analysis of Multi-Megabyte Secondary CPU Cache Memories. TR 1032, Computer Sciences Department, UW-Madison, Madison, WI, July 1991.
[23]
R. E. Kessler, R. Jooss, A. Lebeek, and M. D. Hill. Inexpensive implementations of set-associativity. Proceedings of the 16th dnnual International Symposium on Computer Architecture, 17(3): 13 I-139, 1989.
[24]
S. McFarling. Program optimization for instruction caches. In Proceedings oft he Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III), pages 183-191, April 1989.
[25]
K. McKinley, S. Cart, and C. Tseng. Improving data locality with loop transformations. Transactions on Programming Languages and Systems, 18(4), July 1996.
[26]
P. Panda, N. Dutt, and A. Nieolau. Memory data organization for improved cache performance in embedded processor applications. Transactions on Design Automation of Electronic Systems, 2(4), October 1997.
[27]
J. Peir, Y. Lee, and W. Hsu. Capturing dynamic memory reference behavior with adaptive cache topology. In ~igth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.
[28]
K. Pettis and R. C. Hansen. Profile guided code positioning. Proceedings oft he SIGPLAN '90 ConJ~rence on Programming Language Design and Implementation, 25(6): 16-27, June 1990.
[29]
G. Rivera and C.-W. Tseng. Data transformations for eliminating conflict misses. In Proceedings of the SIGPLAN '98 Conj~rence on Programming Language Design and Implementation, June 1998.
[30]
T. Romer, D. Lee, B. Bershad, and J.B Chen. Dynamic page mapping policies for cache conflict resolution on standard hardware. In Proceedings of the 1st Symposium on Operatingy Systems Design and Implemenation, pages 255-266, November 1994.
[31]
A. Srivastava and A. Eustaee. ATOM: A system for building customized program analysis tools. In Proceedings of the Conference on Programming Language Design and Implementation, pages 196-205. ACM, 1994.
[32]
D.M. Tullsen, S.J. Eggers, and H.M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In 22nd Annual International Symposium on Computer Architecture, pages 392-403, June 1995.
[33]
G. Tyson and M. Fattens. Managing data caches using selective cache line replacement. International Journal of Parallel Programming, 25(3), June 1997.
[34]
S. J.E. Wilton and N. P. Jouppi. An enhanced access and cycle time model for on-chip caches. Teeh report 93/5, DEC Western Research Lab, 1994.
[35]
Y. Yamada, J. Gyllenhaal, G.Haab, and W. W. Hwu, Data relocation and prefetching for large data sets. In 27th international Symposium on Microarchitecture, pages 118-127, December 1994.

Cited By

View all
  • (2023)Real-Time USB Networking and Device I/OACM Transactions on Embedded Computing Systems10.1145/360442922:4(1-38)Online publication date: 12-Jun-2023
  • (2023)SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2022.314428720:1(827-840)Online publication date: 1-Jan-2023
  • (2021)CacheInspectorACM Transactions on Architecture and Code Optimization10.1145/345737318:3(1-25)Online publication date: 8-Jun-2021
  • Show More Cited By

Index Terms

  1. Reducing cache misses using hardware and software page placement

                        Recommendations

                        Comments

                        Please enable JavaScript to view thecomments powered by Disqus.

                        Information & Contributors

                        Information

                        Published In

                        cover image ACM Conferences
                        ICS '99: Proceedings of the 13th international conference on Supercomputing
                        June 1999
                        509 pages
                        ISBN:158113164X
                        DOI:10.1145/305138
                        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

                        Sponsors

                        Publisher

                        Association for Computing Machinery

                        New York, NY, United States

                        Publication History

                        Published: 01 May 1999

                        Permissions

                        Request permissions for this article.

                        Check for updates

                        Qualifiers

                        • Article

                        Conference

                        ICS99
                        Sponsor:

                        Acceptance Rates

                        ICS '99 Paper Acceptance Rate 57 of 180 submissions, 32%;
                        Overall Acceptance Rate 629 of 2,180 submissions, 29%

                        Contributors

                        Other Metrics

                        Bibliometrics & Citations

                        Bibliometrics

                        Article Metrics

                        • Downloads (Last 12 months)79
                        • Downloads (Last 6 weeks)13
                        Reflects downloads up to 19 Dec 2024

                        Other Metrics

                        Citations

                        Cited By

                        View all
                        • (2023)Real-Time USB Networking and Device I/OACM Transactions on Embedded Computing Systems10.1145/360442922:4(1-38)Online publication date: 12-Jun-2023
                        • (2023)SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2022.314428720:1(827-840)Online publication date: 1-Jan-2023
                        • (2021)CacheInspectorACM Transactions on Architecture and Code Optimization10.1145/345737318:3(1-25)Online publication date: 8-Jun-2021
                        • (2021)10 Years Later: Cloud Computing is Closing the Performance GapCompanion of the ACM/SPEC International Conference on Performance Engineering10.1145/3447545.3451183(41-48)Online publication date: 19-Apr-2021
                        • (2021)DRLPartProceedings of the 30th International Symposium on High-Performance Parallel and Distributed Computing10.1145/3431379.3460648(175-188)Online publication date: 21-Jun-2021
                        • (2021)LFOC+: A Fair OS-level Cache-Clustering Policy for Commodity Multicore SystemsIEEE Transactions on Computers10.1109/TC.2021.3112970(1-1)Online publication date: 2021
                        • (2021)CoPlace: Effectively Mitigating Cache Conflicts in Modern CloudsProceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT52795.2021.00027(274-288)Online publication date: 26-Sep-2021
                        • (2020)Reexamining direct cache access to optimize I/O intensive applications for multi-hundred-gigabit networksProceedings of the 2020 USENIX Conference on Usenix Annual Technical Conference10.5555/3489146.3489192(673-689)Online publication date: 15-Jul-2020
                        • (2019)LFOCProceedings of the 48th International Conference on Parallel Processing10.1145/3337821.3337925(1-10)Online publication date: 5-Aug-2019
                        • (2019)Make the Most out of Last Level Cache in Intel ProcessorsProceedings of the Fourteenth EuroSys Conference 201910.1145/3302424.3303977(1-17)Online publication date: 25-Mar-2019
                        • Show More Cited By

                        View Options

                        View options

                        PDF

                        View or Download as a PDF file.

                        PDF

                        eReader

                        View online with eReader.

                        eReader

                        Login options

                        Media

                        Figures

                        Other

                        Tables

                        Share

                        Share

                        Share this Publication link

                        Share on social media