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research-article

A novel unified dummy fill insertion framework with SQP-based optimization method

Authors:

Sheng-Guo Wang,

Xuan ZengAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/2966986.2966994

Published: 07 November 2016 Publication History

Abstract

Dummy fill insertion is widely applied to significantly improve the planarity of topographic patterns for chemical mechanical polishing process in VLSI manufacture. However, these dummies will lead to additional parasitic capacitance and deteriorate the circuit performance. The main challenge of dummy filling algorithms is how to balance multiple objectives, such as fill amount, density variation, parasitic capacitance, etc. which is the aim of ICCAD 2014 DFM contest. Traditional dummy fill insertion methods are no longer applicable because they generate large amount of fills or take unaffordable time. In this paper, we propose a unified dummy fill insertion optimization framework based on multi-starting points and sequential quadratic programming optimization solver, where all objectives are considered simultaneously without approximation. Selecting the initial points smartly with prior knowledge, the proposed method can be effectively accelerated. Even without any prior knowledge, it can also reach high fill quality by random initial points with high scalability. The proposed algorithm is verified by ICCAD 2014 DFM contest benchmark, which shows better quality of dummy filling over the state-of-the-art algorithms.

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Cited By

Zhang BZhen LWang SYang F(2024)Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A ReviewAsia-Pacific Journal of Operational Research10.1142/S021759592450007641:06Online publication date: 6-Jul-2024
https://doi.org/10.1142/S0217595924500076
Chen ZCai JYan CBi ZMa YYu BHu WZhou DZeng X(2024)pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter AdjustmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332062943:2(667-680)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3320629
Bai XZhu ZLi PChen JLan TLi XYu JZhu WChang Y(2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3133854
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2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Copyright © 2016.

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IEEE Press

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Published: 07 November 2016

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Cited By

Zhang BZhen LWang SYang F(2024)Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A ReviewAsia-Pacific Journal of Operational Research10.1142/S021759592450007641:06Online publication date: 6-Jul-2024
https://doi.org/10.1142/S0217595924500076
Chen ZCai JYan CBi ZMa YYu BHu WZhou DZeng X(2024)pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter AdjustmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332062943:2(667-680)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3320629
Bai XZhu ZLi PChen JLan TLi XYu JZhu WChang Y(2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3133854
Cai JYan CTao YLin YWang SPan DZeng X(2021)A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization MethodIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300138040:3(603-607)Online publication date: Mar-2021
https://doi.org/10.1109/TCAD.2020.3001380
Cai JYan CMa YYu BZhou DZeng X(2021)NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586325(187-192)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586325
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Wu ZSavidis ISchlichtmann UGal RAmrouch HLi H(2020)CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit SizingProceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3380446.3430633(49-54)Online publication date: 16-Nov-2020
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Yu SKao CHuang CJiang ICheng KYang H(2020)Equivalent Capacitance Guided Dummy Fill Insertion for Timing and ManufacturabilityProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045668(133-138)Online publication date: 17-Jan-2020
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GENG CLIU BNAKATAKE S(2019)Density Optimization for Analog Layout Based on Transistor-ArrayIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E102.A.1720E102.A:12(1720-1730)Online publication date: 1-Dec-2019
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