More Web Proxy on the site http://driver.im/

research-article

A novel unified dummy fill insertion framework with SQP-based optimization method

Authors:

Sheng-Guo Wang,

Xuan ZengAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/2966986.2966994

Published: 07 November 2016 Publication History

Abstract

Dummy fill insertion is widely applied to significantly improve the planarity of topographic patterns for chemical mechanical polishing process in VLSI manufacture. However, these dummies will lead to additional parasitic capacitance and deteriorate the circuit performance. The main challenge of dummy filling algorithms is how to balance multiple objectives, such as fill amount, density variation, parasitic capacitance, etc. which is the aim of ICCAD 2014 DFM contest. Traditional dummy fill insertion methods are no longer applicable because they generate large amount of fills or take unaffordable time. In this paper, we propose a unified dummy fill insertion optimization framework based on multi-starting points and sequential quadratic programming optimization solver, where all objectives are considered simultaneously without approximation. Selecting the initial points smartly with prior knowledge, the proposed method can be effectively accelerated. Even without any prior knowledge, it can also reach high fill quality by random initial points with high scalability. The proposed algorithm is verified by ICCAD 2014 DFM contest benchmark, which shows better quality of dummy filling over the state-of-the-art algorithms.

7. References

[1]

P. T. Boggs and J. W. Tolle. Sequential quadratic programming. Acta Numerica, 4 (1): 1–51, January 1995.

[2]

Y. Chen, P. Gupta, and A. B. Kahng. Performance-impact limited area fill synthesis. In Proc. ACM/IEEE Des. Autom. Conf. pages 22–27, 2003.

[3]

Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky. Monte-carlo algorithms for layout density control. In Proc. IEEE Asia South Pacific Des. Autom. Coif., pages 523–528, 2000.

[4]

Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky. Practical iterated fill synthesis for cmp uniformity. In Proc. ACM/IEEE Des. Autom. Conf. pages 671–674, 2000.

[5]

C. Feng, H. Zhou, C. Yan J. Tao, and X. Zeng. Provably good and practically efficient algorithms for cmp dummy fill. In Proc. ACM/IEEE Des. Autom. Conf. pages 539–544, 2009.

[6]

C. Feng, H. Zhou, C. Yan, J. Tao, and X. Zeng. Efficient approximation algorithms for chemical mechanical polishing dummy fill. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 30 (3): 402–415, March 2011.

Digital Library

[7]

K. D. Gourley and D. M. Green. Polygon-to-rectangle conversion algorithm. IEEE Comp. Graphics & Applic., 3 (1): 31–36, January 1983.

Digital Library

[8]

A. B. Kahng, G. Robins, A. Singn, and A. Zelikovsky. Filling algorithms and analyses for layout density control. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 18 (4): 1132–1147, October 2002.

[9]

A. B. Kahng and K. Samadi. Cmp fill synthesis: A survey of recent studies. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 27 (1): 3–19, January 2008.

[10]

A. B. Kahng and R. O. Topaloglu. A doe set for normalization-based extraction of fill impact on capacitances. In Proc. Int. Symp. Quality Electron. Des. pages 467–474, 2007.

[11]

W. S. Lee, K. H. Lee, J. K. Park, T. K. Kim, Y. K. Park, and J. T. Kong. Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling. In Proc. Int. Symp. Quality Electron. Des., pages 373–376, 2003.

[12]

Y. Lin, B. Yu, and D. Z. Pan. High performance dummy fill insertion with coupling and uniformity constraints. In Proc. ACM/IEEE Des. Autom. Conf., pages 1–6, 2015.

[13]

C. Liu, Peishan Tu, P. Wu, H. Tang, Y. Jiang, J. Kuang, and E. F. Y. Young. An effective chemical mechanical polishing filling approach. In Proc. IEEE Comput. Soc. Annual Sym. VLSI, pages 44–49, 2015.

[14]

S. Sinha, J. Luo, and C. Chiang. Model based layout pattern dependent metal filling algorithm for improved chip surface uniformity in the copper process. In Proc. IEEE Asia South Pacific Des. Autom. Conf. pages 1–6, 2007.

[15]

R. Tian, D. F. Wong, and R. Boone. Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 20 (7): 902–910, July 2001.

Digital Library

[16]

R. O. Topaloglu. Energy-minimization model for fill synthesis. In Proc. Int. Symp. Quality Electron. Des., pages 444–451, 2007.

[17]

R. O. Topaloglu. Iccad-2014 cad contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite. In Proc. IEEE Int. Conf. Comput.-Aided Des., pages 367–368, 2014.

[18]

X. Wang, C. C. Chiang, J. Kawa, and Q. Su. A min-variance iterative method for fast smart dummy feature density assignment in chemical-mechanical polishing. In Proc. Int. Symp. Quality Electron. Des., pages 258–263, 2005.

[19]

H. Xiang, L. Deng, R. Puri, K.-Y. Chao, and M. D. F. Wong. Fast dummy-fill density analysis with coupling constraints. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 27 (4): 633–642, April 2008.

Digital Library

Cited By

Chen ZCai JYan CBi ZMa YYu BHu WZhou DZeng X(2024)pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter AdjustmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332062943:2(667-680)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3320629
Bai XZhu ZLi PChen JLan TLi XYu JZhu WChang Y(2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3133854
Cai JYan CTao YLin YWang SPan DZeng X(2021)A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization MethodIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300138040:3(603-607)Online publication date: Mar-2021
https://doi.org/10.1109/TCAD.2020.3001380
Show More Cited By

Index Terms

A novel unified dummy fill insertion framework with SQP-based optimization method

Index terms have been assigned to the content through auto-classification.

Recommendations

Dummy fill optimization for enhanced manufacturability
ISPD '10: Proceedings of the 19th international symposium on Physical design

This paper presents a router that minimizes the amount of dummy fill necessary to satisfy the requirements for chemical-mechanical polishing (CMP). The algorithm uses a greedy strategy and effective cost functions to control the maximal effective ...
Dummy fill aware buffer insertion during routing
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

This paper studies the impacts of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion during routing. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in ...
High performance dummy fill insertion with coupling and uniformity constraints
DAC '15: Proceedings of the 52nd Annual Design Automation Conference

In deep-submicron VLSI manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Guide Proceedings

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Copyright © 2016.

Publisher

IEEE Press

Publication History

Published: 07 November 2016

Permissions

Request permissions for this article.

Request Permissions

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
81
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Chen ZCai JYan CBi ZMa YYu BHu WZhou DZeng X(2024)pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter AdjustmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332062943:2(667-680)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3320629
Bai XZhu ZLi PChen JLan TLi XYu JZhu WChang Y(2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3133854
Cai JYan CTao YLin YWang SPan DZeng X(2021)A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization MethodIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300138040:3(603-607)Online publication date: Mar-2021
https://doi.org/10.1109/TCAD.2020.3001380
Cai JYan CMa YYu BZhou DZeng X(2021)NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586325(187-192)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586325
Chen JZhu ZZhu WYao-Wen C(2020)A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit LegalizationACM Transactions on Design Automation of Electronic Systems10.1145/342332626:2(1-28)Online publication date: 10-Dec-2020
https://dl.acm.org/doi/10.1145/3423326
Wu ZSavidis ISchlichtmann UGal RAmrouch HLi H(2020)CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit SizingProceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3380446.3430633(49-54)Online publication date: 16-Nov-2020
https://dl.acm.org/doi/10.1145/3380446.3430633
Yu SKao CHuang CJiang ICheng KYang H(2020)Equivalent Capacitance Guided Dummy Fill Insertion for Timing and ManufacturabilityProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045668(133-138)Online publication date: 17-Jan-2020
https://dl.acm.org/doi/10.1109/ASP-DAC47756.2020.9045668
GENG CLIU BNAKATAKE S(2019)Density Optimization for Analog Layout Based on Transistor-ArrayIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E102.A.1720E102.A:12(1720-1730)Online publication date: 1-Dec-2019
https://doi.org/10.1587/transfun.E102.A.1720
Chen JZhu ZZhu WChang Y(2017)Toward Optimal Legalization for Mixed-Cell-Height Circuit DesignsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062330(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062330
Geng CLiu BNakatake S(2017)Explicit layout pattern density controlling based on transistor-array-style2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053233(1557-1560)Online publication date: Aug-2017
https://doi.org/10.1109/MWSCAS.2017.8053233

View Options

View options

Media

Figures

Other

Tables

View Table of Contents