More Web Proxy on the site http://driver.im/

research-article

MTJ variation monitor-assisted adaptive MRAM write

Authors:

Pedram Khalili,

Puneet GuptaAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 169, Pages 1 - 6

https://doi.org/10.1145/2897937.2897979

Published: 05 June 2016 Publication History

Abstract

Spin-transfer torque random access memory (STT-RAM) and magnetoelectric random access memory (MeRAM) are promising non-volatile memory technologies. But STT-RAM and Me RAM both suffer from high write error rate due to thermal fluctuation of magnetization. Temperature and wafer-level process variation significantly exacerbate these problems. In this paper, we propose a design that adaptively selects optimized write pulse for STT-RAM and MeRAM to overcome ambient process and temperature variation. To enable the adaptive write, we design specific MTJ-based variation monitor, which precisely senses process and temperature variation. The monitor is over 10X faster, 5X more energy-efficient, and 20X smaller compared with conventional thermal monitors of similar accuracy. With adaptive write, the write latency of STT-RAM and MeRAM cache are reduced by up to 17% and 59% respectively, and application run time is improved by up to 41%.

References

[1]

S. Tehrani et al. "Progress and outlook for MRAM technology". TMAG (1999).

[2]

C. Heide. "Spin currents in magnetic films". Phys. Rev. Lett. (2001).

[3]

D. Worledge et al. "Spin torque switching of perpendicular Ta| CoFeB| MgO-based magnetic tunnel junctions". Appl. Phys. Lett. (2011).

[4]

C. W. Smullen et al. "Relaxing non-volatility for fast and energy-efficient STT-RAM caches". HPCA. IEEE. 2011.

Digital Library

[5]

A. Jog et al. "Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs". Proc. DAC. ACM. 2012.

Digital Library

[6]

E. Kultursay et al. "Evaluating STT-RAM as an energy-efficient main memory alternative". ISPASS. IEEE. 2013.

[7]

S. Kanai et al. "Electric field-induced magnetization reversal in a perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction". Appl. Phys. Lett. (2012).

[8]

Y. Shiota et al. "Induction of coherent magnetization switching in a few atomic layers of FeCo using voltage pulses". Nature materials (2012).

[9]

W.-G. Wang et al. "Electric-field-assisted switching in magnetic tunnel junctions". Nature materials (2012).

[10]

J. Li et al. "Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement". Proc. CICC. IEEE. 2008.

[11]

P. Wang et al. "A thermal and process variation aware MTJ switching model and its applications in soft error analysis". Proc. ICCAD. IEEE. 2012.

Digital Library

[12]

S. Wang et al. "Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory". IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2016).

[13]

Y. Eckert, N. Jayasena, and G. Loh. "Thermal feasibility of die-stacked processing in memory". Proceedings of the 2nd Workshop on Near-Data Processing. 2014.

[14]

J.-Y. Park et al. "Etching of CoFeB Using CO/NH3 in an Inductively Coupled Plasma Etching System". J. Electrochem. Soc (2011).

[15]

R. W. Dave et al. "MgO-based tunnel junction material for high-speed toggle magnetic random access memory". TMAG (2006).

[16]

J. Slaughter et al. "Magnetic tunnel junction materials for electronic applications". JOM(USA) (2000).

[17]

R. Sbiaa et al. "Reduction of switching current by spin transfer torque effect in perpendicular anisotropy magnetoresistive devices". J. Appl. Phys. (2011).

[18]

Y. Zhang et al. "Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions". TED (2012).

[19]

K. Lee, O. Redon, and B. Dieny. "Analytical investigation of spin-transfer dynamics using a perpendicular-to-plane polarizer". Appl. Phys. Lett. (2005).

[20]

Y. Zhang, X. Wang, and Y. Chen. "STT-RAM cell design optimization for persistent and non-persistent error rate reduction: a statistical design view". Proc. ICCAD. IEEE. 2011.

Digital Library

[21]

J.-W. Jang et al. "Self-correcting STTRAM under magnetic field attacks". DAC. IEEE. 2015.

Digital Library

[22]

P. Zhou et al. "Energy reduction for STT-RAM using early write termination". ICCAD. IEEE. 2009.

Digital Library

[23]

Y. M. Lee et al. "Giant tunnel magnetoresistance and high annealing stability in CoFeB/MgO/CoFeB magnetic tunnel junctions with synthetic pinned layer". arXiv preprint cond-mat/0606503 (2006).

[24]

J. G. Alzate et al. "Temperature dependence of the voltage-controlled perpendicular anisotropy in nanoscale MgO| CoFeB| Ta magnetic tunnel junctions". Appl. Phys. Lett. (2014).

[25]

S. Wang et al. "Evaluation of digital circuit-level variability in inversion-mode and junctionless FinFET technologies". TED (2013).

[26]

C.-C. Chung and C.-R. Yang. "An autocalibrated all-digital temperature sensor for on-chip thermal monitoring". TCS (2011).

[27]

K. Woo et al. "Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring". ISSCC. IEEE. 2009.

[28]

P. Chen et al. "A time-domain SAR smart temperature sensor with curvature compensation and a 3σ inaccuracy of −0.4 C + 0.6 C over a 0 C to 90 C range". JSSC (2010).

[29]

A. L. Aita et al. "A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25 C (3σ) from- 70 C to 130 C". ISSCC. IEEE. 2009.

[30]

P. K. Amiri et al. "Electric-field-induced thermally assisted switching of monodomain magnetic bits". J. Appl. Phys. (2013).

[31]

Y. Higo et al. "Thermal activation effect on spin transfer switching in magnetic tunnel junctions". Appl. Phys. Lett. (2005).

[32]

H. Lee et al. "Design of a Fast and Low-Power Sense Amplifier and Writing Circuit for High-Speed MRAM". TMAG (2015).

[33]

X. Dong et al. "Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory". ICCAD (2012).

[34]

N. Binkert et al. "The gem5 simulator". ACM SIGARCH Computer Architecture News (2011).

Digital Library

[35]

S. Li et al. "McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures". MICRO. IEEE. 2009.

Digital Library

[36]

W. Huang et al. "HotSpot: A compact thermal modeling methodology for early-stage VLSI design". TVLSI (2006).

Digital Library

Cited By

Yuan SXun HKim WRao SMarinissen ECouet SFieback MTaouil MHamdioui S(2024)Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?2024 IEEE International Test Conference (ITC)10.1109/ITC51657.2024.00058(364-373)Online publication date: 3-Nov-2024
https://doi.org/10.1109/ITC51657.2024.00058
Hu CAn ZZhou TWan CXu CZhu A(2023)A Low-Power, High-Speed Auto-Terminated Write Circuit Architecture With Hybrid MTJ/CMOS CircuitsIEEE Transactions on Magnetics10.1109/TMAG.2023.323610859:3(1-6)Online publication date: Mar-2023
https://doi.org/10.1109/TMAG.2023.3236108
Sin SOh S(2023)Deterministic field-free voltage-induced magnetization switching with self-regulated precession for low-power memoryScientific Reports10.1038/s41598-023-43378-213:1Online publication date: 26-Sep-2023
https://doi.org/10.1038/s41598-023-43378-2
Show More Cited By

Recommendations

Write-optimized reliable design of STT MRAM
ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is ...
Progress and outlook for STT-MRAM
ICCAD '11: Proceedings of the International Conference on Computer-Aided Design

New product applications have an increasing demand for a non-volatile memory (NVM) exhibiting higher speeds, extended endurance and lower power consumption as existing solutions are not fully capable to deliver on all of these attributes. Of the group ...
SLC-enabled Wear Leveling for MLC PCM Considering Process Variation
DAC '14: Proceedings of the 51st Annual Design Automation Conference

Phase change memory is becoming one of the most promising candidates to replace DRAM as main memory in deep silicon regime. Multi-level cell (MLC) PCM outperforms single level cell (SLC) in terms of capacity while suffering from a weaker cell endurance. ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2016

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

15
Total Citations
View Citations
263
Total Downloads

Downloads (Last 12 months)26
Downloads (Last 6 weeks)3

Reflects downloads up to 19 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Yuan SXun HKim WRao SMarinissen ECouet SFieback MTaouil MHamdioui S(2024)Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?2024 IEEE International Test Conference (ITC)10.1109/ITC51657.2024.00058(364-373)Online publication date: 3-Nov-2024
https://doi.org/10.1109/ITC51657.2024.00058
Hu CAn ZZhou TWan CXu CZhu A(2023)A Low-Power, High-Speed Auto-Terminated Write Circuit Architecture With Hybrid MTJ/CMOS CircuitsIEEE Transactions on Magnetics10.1109/TMAG.2023.323610859:3(1-6)Online publication date: Mar-2023
https://doi.org/10.1109/TMAG.2023.3236108
Sin SOh S(2023)Deterministic field-free voltage-induced magnetization switching with self-regulated precession for low-power memoryScientific Reports10.1038/s41598-023-43378-213:1Online publication date: 26-Sep-2023
https://doi.org/10.1038/s41598-023-43378-2
Sethuraman STavva VSrinivas M(2022)Techniques to Improve Write and Retention Reliability of STT-MRAM Memory SubsystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.311821041:9(2901-2914)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3118210
Tatulian ADeMara R(2022)Generalized Exponentiation Using STT Magnetic Tunnel Junctions: Circuit Design, Performance, and Application to Neural Network Gradient DecaySN Computer Science10.1007/s42979-022-01039-73:2Online publication date: 31-Jan-2022
https://doi.org/10.1007/s42979-022-01039-7
Wang SLee HGrezes CAmiri PWang KGupta P(2021)Adaptive MRAM Write and Read with MTJ Variation MonitorIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2018.28662899:1(402-413)Online publication date: 1-Jan-2021
https://doi.org/10.1109/TETC.2018.2866289
Natsui MTamakoshi AHonjo HWatanabe TNasuno TZhang CTanigawa TInoue HNiwa MYoshiduka TNoguchi YYasuhira MMa YShen HFukami SSato HIkeda SOhno HEndoh THanyu T(2021)Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free ConditionIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.303980056:4(1116-1128)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3039800
Sethuraman STavva VRajamani KSubramanian CKim KHunter HSrinivas M(2020)Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory SubsystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2982134(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.2982134
Wu BDai PCheng YWang YYang JWang ZLiu DZhao W(2020)A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal ConsiderationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289770739:4(803-815)Online publication date: Apr-2020
https://doi.org/10.1109/TCAD.2019.2897707
Long MZeng LGao TZhang DQin XZhang YZhao W(2018)Self-Adaptive Write Circuit for Magnetic Tunneling Junction Memory With Voltage-Controlled Magnetic Anisotropy EffectIEEE Transactions on Nanotechnology10.1109/TNANO.2018.281572117:3(492-499)Online publication date: May-2018
https://doi.org/10.1109/TNANO.2018.2815721
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents