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RunStream: A High-Level Rapid Prototyping Framework for Stream Ciphers

Published: 06 June 2016 Publication History

Abstract

We present RunStream, a rapid prototyping framework for realizing stream cipher implementations based on algorithmic specifications and architectural customizations desired by the users. In the dynamic world of cryptography where newer recommendations are frequently proposed, the need of such tools is imperative. It carries out design validation and generates an optimized software implementation and a synthesizable Register Transfer Level Verilog description. Our framework enables speedy benchmarking against critical resources like area, throughput, power, and latency and allows exploration of alternatives. Using RunStream, we successfully implemented various stream ciphers and benchmarked the quality of results to be at par with published hand-optimized implementations.

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Cited By

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  • (2020)Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3IEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.2997916(1-14)Online publication date: 2020
  • (2019)High Level Synthesis for Symmetric Key CryptographyDomain Specific High-Level Synthesis for Cryptographic Workloads10.1007/978-981-10-1070-5_4(51-90)Online publication date: 29-Mar-2019
  • (2019)IntroductionDomain Specific High-Level Synthesis for Cryptographic Workloads10.1007/978-981-10-1070-5_1(1-4)Online publication date: 29-Mar-2019

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    cover image ACM Transactions on Embedded Computing Systems
    ACM Transactions on Embedded Computing Systems  Volume 15, Issue 3
    July 2016
    520 pages
    ISSN:1539-9087
    EISSN:1558-3465
    DOI:10.1145/2899033
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Publication History

    Published: 06 June 2016
    Accepted: 01 February 2016
    Revised: 01 December 2015
    Received: 01 July 2015
    Published in TECS Volume 15, Issue 3

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    Author Tags

    1. Hardware generation
    2. eSTREAM
    3. high-level synthesis
    4. rapid prototyping
    5. stream cipher

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    View all
    • (2020)Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3IEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.2997916(1-14)Online publication date: 2020
    • (2019)High Level Synthesis for Symmetric Key CryptographyDomain Specific High-Level Synthesis for Cryptographic Workloads10.1007/978-981-10-1070-5_4(51-90)Online publication date: 29-Mar-2019
    • (2019)IntroductionDomain Specific High-Level Synthesis for Cryptographic Workloads10.1007/978-981-10-1070-5_1(1-4)Online publication date: 29-Mar-2019

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