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DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout

Authors:

Shigetoshi Nakatake,

Bo YangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 3

Article No.: 45, Pages 1 - 21

https://doi.org/10.1145/2888395

Published: 11 May 2016 Publication History

Abstract

In the MOS analog layout, variability suppression is becoming a major issue, as is layout efficiency. Introducing a transistor array (TA) style to analog layout, this article addresses the layout-dependent variability based on the measurement results of test chips on 90nm CMOS process. In TA style, a large transistor is decomposed into a set of unified subtransistors, which are connected in series or parallel. Focusing on one row layout of diffusion sharing for the multiple gates, we analyze the current direction-dependent variability and the leakage current via off-gates for the electrical isolation. Furthermore, we present several analog design cases on TA including analysis of the impact on the DC characteristics caused by the transistor channel decomposition.

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Cited By

Mirhosseini MFazlali MFallah MLee J(2023)A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithmThe Journal of Supercomputing10.1007/s11227-023-05109-279:11(12042-12073)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1007/s11227-023-05109-2
Liu BHuang ZZhang JLiu MMeng Q(2020)A full-transistor fine-grain multilevel delay element with compact regularity layoutAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01588-y103:1(163-172)Online publication date: 3-Feb-2020
https://dl.acm.org/doi/10.1007/s10470-020-01588-y
GENG CLIU BNAKATAKE S(2019)Density Optimization for Analog Layout Based on Transistor-ArrayIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E102.A.1720E102.A:12(1720-1730)Online publication date: 1-Dec-2019
https://doi.org/10.1587/transfun.E102.A.1720
Show More Cited By

Index Terms

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Physical synthesis
      2. Placement

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Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 3

Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers

July 2016

434 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2926747

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 11 May 2016

Accepted: 01 January 2016

Revised: 01 November 2015

Received: 01 July 2015

Published in TODAES Volume 21, Issue 3

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Variability-Tolerant Analog LSI Design Methodology Based on Fine Grain Transistor Array
Semiconductor Technology Academic Research Center (STARC)

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Cited By

Mirhosseini MFazlali MFallah MLee J(2023)A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithmThe Journal of Supercomputing10.1007/s11227-023-05109-279:11(12042-12073)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1007/s11227-023-05109-2
Liu BHuang ZZhang JLiu MMeng Q(2020)A full-transistor fine-grain multilevel delay element with compact regularity layoutAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01588-y103:1(163-172)Online publication date: 3-Feb-2020
https://dl.acm.org/doi/10.1007/s10470-020-01588-y
GENG CLIU BNAKATAKE S(2019)Density Optimization for Analog Layout Based on Transistor-ArrayIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E102.A.1720E102.A:12(1720-1730)Online publication date: 1-Dec-2019
https://doi.org/10.1587/transfun.E102.A.1720
Liu BChen GYang BNakatake S(2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
https://dl.acm.org/doi/10.1145/3182169
Geng CLiu BNakatake S(2017)Explicit layout pattern density controlling based on transistor-array-style2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053233(1557-1560)Online publication date: Aug-2017
https://doi.org/10.1109/MWSCAS.2017.8053233
Nanri ALiu BNakatake S(2016)Layout-dependent effect evaluation of transistor array-style phase locked loop2016 IEEE Region 10 Conference (TENCON)10.1109/TENCON.2016.7848449(2346-2349)Online publication date: Nov-2016
https://doi.org/10.1109/TENCON.2016.7848449

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