Reducing Transistor Variability for High Performance Low Power Chips

Fluctuations in intrinsic linear V_t, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic σV_T, free of extrinsic process, length and width variations, is random, ...

The very large scale integrated (VLSI) circuits become susceptible to soft errors mainly due to exposure to harsh environmental conditions. In this paper, the analysis of total ionizing dose (TID) effects on single gate NMOS, enclosed ...

Designing a microprocessor that's efficient across a wide-voltage-operating range requires overcoming a variety of microarchitecture and circuit design challenges. In this article, the authors demonstrate their IA-32 processor, which is built in 32-nm ...