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MetaCore: an application specific DSP development system

Published: 01 May 1998 Publication History

Abstract

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.
MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.

References

[1]
E. A. Lee, "Programmable DSPs: a Brief Overview", IEEE Micro, Oct. 1990, Vol. 10, No. 5, pp. 14-16.
[2]
G. Intrater, D. Biran, "Application Specific Microprocessors'', Proc. IEEE Int'l Conference on Computer Design: VLSI in Computers ~ Processors, 1990.
[3]
R. Woudsma, R. A. M. Beltman, et al.,"EPICS, a Flexible Approach to Embedded DSP Cores", Proc.{nt'l Conference on Signal Processing Applications ~4 Technology (ICSPAD, Oct. 1994, pp. 506-511.
[4]
Jun Sato, et al., "PEAS-I: A Hardware/Software Codesign System for ASIP Development", IEICE Trans. Fundamentals, Mar. 1994, pp. 483-491.
[5]
Mario R. Barbacci, "Instruction Set Processor Specifications(ISPS): The Notation and Its Applications", IEEE Trans. CAD, Jan. 1981, pp. 24-40.
[6]
G. Kane. MIPS RISC architecture, Prentice-Hall, 1989.

Cited By

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  • (2014)Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operationsMicroprocessors and Microsystems10.1016/j.micpro.2014.06.00238:7(707-716)Online publication date: Oct-2014
  • (2006)Customization of application specific heterogeneous multi-pipeline processorsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131693(746-751)Online publication date: 6-Mar-2006
  • (2004)Instruction set and functional unit synthesis for SIMD processor coresProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015291(743-750)Online publication date: 27-Jan-2004
  • Show More Cited By

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Published In

cover image ACM Conferences
DAC '98: Proceedings of the 35th annual Design Automation Conference
May 1998
820 pages
ISBN:0897919645
DOI:10.1145/277044
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 May 1998

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Author Tags

  1. high-level synthesis
  2. telecommunication

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DAC98
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DAC98: The 35th ACM/IEEE-CAS/EDAC Design Automation Conference
June 15 - 19, 1998
California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2014)Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operationsMicroprocessors and Microsystems10.1016/j.micpro.2014.06.00238:7(707-716)Online publication date: Oct-2014
  • (2006)Customization of application specific heterogeneous multi-pipeline processorsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131693(746-751)Online publication date: 6-Mar-2006
  • (2004)Instruction set and functional unit synthesis for SIMD processor coresProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015291(743-750)Online publication date: 27-Jan-2004
  • (2004)Dual-pipeline heterogeneous ASIP designProceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1016720.1016727(12-17)Online publication date: 8-Sep-2004
  • (2004)Instruction set and functional unit synthesis for SIMD processor coresASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)10.1109/ASPDAC.2004.1337692(743-750)Online publication date: 2004
  • (2003)INSIDEProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009905Online publication date: 9-Nov-2003
  • (2003)Rapid Configuration and Instruction Selection for an ASIPProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022823Online publication date: 3-Mar-2003
  • (2003)INSIDE: INstruction Selection/Identification & Design Exploration for extensible processorsICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)10.1109/ICCAD.2003.159703(291-297)Online publication date: 2003
  • (2003)Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03).10.1109/ICASSP.2003.1202409(II-485-8)Online publication date: 2003
  • (2003)Rapid configuration and instruction selection for an ASIP: a case study2003 Design, Automation and Test in Europe Conference and Exhibition10.1109/DATE.2003.1253705(802-807)Online publication date: 2003
  • Show More Cited By

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