More Web Proxy on the site http://driver.im/

Article

Rapid Configuration and Instruction Selection for an ASIP: A Case Study

Authors:

Sri ParameswaranAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10802

Published: 03 March 2003 Publication History

Abstract

We present a methodology that maximizes the performance of Tensilica based Application Specific Instruction-set Processor (ASIP) through instruction selection when an area constraint is given. Our approach rapidly selects from a set of pre-fabricated coprocessors/functional units from our library of pre-designed specific instructions (to evaluate our technology we use the Tensilica platform). As a result, we significantly increase application performance while area constraints are satisfied. Our methodology uses a combination of simulation, estimation and a pre-characterised library of instructions, to select the appropriate co-processors and instructions. We report that by selecting the appropriate coprocessors/functional units and specific TIE instructions, the total execution time of complex applications (we study a voice encoder/decoder), an applicationýs performance can be reduced by up to 85% compared to the base implementation. Our estimator used in the system takes typically less than a second to estimate, with an average error rate of 4% (as compared to full simulation, which takes 45 minutes). The total selection process using our methodology takes 3-4 hours, while a full design space exploration using simulation would take several days.

References

[1]

{1} Tensilica Instruction Extension (TIE) Language Reference Manual (For Xtensa T1040 Processor Cores). Tensilica, Inc, 2001.

[2]

{2} Tensilica Instruction Extension (TIE) Language User's Guide (For Xtensa T1040 Processor Cores). Tensilica, Inc, 2001.

[3]

{3} ALOMARY, A., NAKATA, T., HONMA, Y., IMAI, M., AND HIKICHI, N. An asip instruction set optimization algorithm with functional module sharing constraint. In ICCAD (1993), pp. 526-532.

Digital Library

[4]

{4} BINH, N., IMAI, M., AND TAKEUCHI, Y. A performance maximization algorithm to design asips under the constraint of chip area including ram and rom size. In ASP-DAC (1998).

[5]

{5} CHOI, H., AND PARK, I. Coware pipelining for exploiting intellectual properties and software codes in processor-based design. In 13th Annual IEEE International ASIC/SOC (2000), pp. 153-157.

[6]

{6} FAUTH, A. Beyond tool-specific macine description. Code Generation for Embedded Processors (1995), 138-152.

[7]

{7} GONZALEZ, R. Xtensa: A configurable and extensible processor. IEEE Micro (2000).

Digital Library

[8]

{8} GUPTA, T. V. K., KO, R. E., AND BARUA, R. Compiler-directed customization of asip cores. In 10th International Symposium on Hardware/Software Co-Design (2002).

Digital Library

[9]

{9} GUPTA, T. V. K., SHARMA, P., BALAKRISHNAN, M., AND MALIK, S. Processor evaluation in an embedded systems design environment. In 13th International Conf. on VLSI Design (2000), pp. 98-103.

Digital Library

[10]

{10} GYLLENHAAL, J. C., HWU, W. M., AND RAU, B. R. HMDES Version 2.0 specification. University of Illinois, 1996.

[11]

{11} HADJIYIANNIS, G., RUSSO, P., AND DEVADAS, S. A methodology for accurate performance evaluation in architecture exploration. In DAC (1999), ACM Press, pp. 927-932.

Digital Library

[12]

{12} HALAMBI, A., GRUN, P., GANESH, V., KAHARE, A., DUTT, N., AND NICOLAU, A. Expression: A language for architecture exploration through compiler/simulator retargetability. In DATE 99 (1999), pp. 485-490.

Digital Library

[13]

{13} HOFFMANN, A., KOGEL, T., NOHL, A., BRAUN, G., SCHLIEBUSCH, O., AND WAHLEN, O. A novel methodology for the design of application-specific instruction-set processors (asips) using a machine description language. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, 11 (2001), 1338-1354.

Digital Library

[14]

{14} IMAI, M., BINH, N., AND SHIOMI, A. A new hw/sw partitioning algorithm for synthesizing the highest performance pipelined asips with multiple identical fus. In EURO-VHDL'96 (1996), pp. 126-131.

Digital Library

[15]

{15} JAIN, M. K., WEHMEYER, L., STEINKE, S., MARWEDEL, P., AND BALAKRISHNAN, M. Evaluating register file size in asip design. In 9th international symposium on Hardware/software codesign (2001), pp. 109-114.

Digital Library

[16]

{16} KOBAYASHI, S., MITA, H., TAKEUCHI, Y., AND IMAI, M. Design space exploration for dsp applications using the asip development system peas-iii. In IEEE International Conf. on Acoustics, Speech, and Signal Processing (2002), pp. 3168-3171.

[17]

{17} LEUPERS, R., AND MARWEDEL, P. Retargetable code generation based on structural processor descriptions. In Design Automation for Embedded Systems (1998), pp. 75-108.

[18]

{18} ONION, F., NICOLAU, A., AND DUTT, N. Incorporating compiler feedback into the design of asips. In DATE (95), pp. 508-513.

Digital Library

[19]

{19} PAULIN, P. G., LIEM, C., MAY, T. C., AND SUTAWALA, S. Flexware: A flexible firmware development environment for embedded systems. In Code Generation for Embedded Processors (1995), pp. 65-84.

[20]

{20} YANG, J.-H., KIM, B.-W., ET AL. Metacore: an application specific dsp development system. In DAC (1998), pp. 800-803.

Digital Library

[21]

{21} ZHAO, Q., MESMAN, B., AND BASTEN, T. Practical instruction set design and compiler retargetability using static resource models. In DATE (02), pp. 1021- 1026.

Digital Library

Cited By

Wang CLi XZhang HWang AZhou X(2017)Hot spots profiling and dataflow analysis in custom dataflow computing SoftProcessorsJournal of Systems and Software10.1016/j.jss.2016.07.025125:C(427-438)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.jss.2016.07.025
Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Bauer LShafique MHenkel JRosenstiel WWakabayashi K(2009)MinDegProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629481(335-342)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629481
Show More Cited By

Index Terms

Rapid Configuration and Instruction Selection for an ASIP: A Case Study

Recommendations

Instruction Selection in ASIP Synthesis Using Functional Matching
VLSID '10: Proceedings of the 2010 23rd International Conference on VLSI Design

In embedded systems, Application Specific Instruction Set Processors (ASIPs) are used commonly with the aim to get high performance without losing flexibility. A crucial operation required during ASIP synthesis (in particular, selection of custom ...
Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06: Proceedings of the 20th international conference on Parallel and distributed processing

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional ...
Automatic custom instruction identification for application-specific instruction set processors

The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 March 2003

Check for updates

Qualifiers

Article

Conference

DATE03

Sponsor:

SIGDA

DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

14
Total Citations
View Citations
255
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 09 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Wang CLi XZhang HWang AZhou X(2017)Hot spots profiling and dataflow analysis in custom dataflow computing SoftProcessorsJournal of Systems and Software10.1016/j.jss.2016.07.025125:C(427-438)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.jss.2016.07.025
Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Bauer LShafique MHenkel JRosenstiel WWakabayashi K(2009)MinDegProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629481(335-342)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629481
Lü YShen LWang ZXiao NRosenstiel WWakabayashi K(2009)Dynamically utilizing computation accelerators for extensible processors in a software approachProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629443(51-60)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629443
Bauer LShafique MKreutz SHenkel JSciuto D(2008)Run-time system for an extensible embedded processor with dynamic instruction setProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403558(752-757)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403558
Bauer LShafique MHenkel JFix L(2008)Run-time instruction set selection in a transmutable embedded processorProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391486(56-61)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391486
Bauer LShafique MHenkel J(2008)Efficient resource utilization for an extensible processor through dynamic instruction set adaptationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200243016:10(1295-1308)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2002430
Bauer LShafique MKramer SHenkel JLevitan S(2007)RISPPProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278678(791-796)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278678
Angiolini FCeng JLeupers RFerrari FFerri CBenini LGielen G(2006)An integrated open framework for heterogeneous MPSoC design space explorationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131797(1145-1150)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131797
Sun FRavi SRaghunathan AJha N(2006)A scalable synthesis methodology for application-specific processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641014:11(1175-1188)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.886410
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents