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An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT

Published: 07 June 2015 Publication History

Abstract

Lithography simulation is an essential technique to guide the design of inverse lithography technology (ILT) masks. To reduce the complexity in modern lithography simulation, a widely used approach is to first rasterize the ILT masks before they are inputted to the simulation tools. Currently, there is no high performance technology to handle the rasterization of all-angle polygons, which are very common in modern ILT masks. Traditional rasterization technology is very expensive in term of runtime and memory usage. In this paper, we propose an efficient rasterization algorithm for all-angle polygons based on a pre-computed lookup table (LUT). We expect that the convolution for a majority of large pixels can be performed in a single lookup table query, which decreases the overall runtime dramatically. The experimental results demonstrate that our proposed algorithm can speed up rasterization process by almost 500x while maintaining small variations in CD. Meanwhile, the time for pre-computing the lookup table and the size of it can be kept within very reasonable limits.

References

[1]
Alfred Kwok-Kit Wong. Optical Imaging in Projection Microlithography, volume 66 of SPIE Tutorial Texts. SPIE Publications, Vancouver, Washington, 2005.
[2]
Yong Liu, Dan Abrams, Linyong Pang, and Andrew Moore. Inverse lithography technology principles in practice: unintuitive patterns. In Proc. of SPIE 5992, 2005.
[3]
Michael L. Rieger, Micheal Cranford, and John P. Stirniman. Flash-based anti-aliasing techniques for high-accuracy high-efficiency mask synthesis, Jan 2011. Patent.
[4]
John F. Hughes, Andries van Dam, and et al. Computer Graphics: Principles and Practice (3rd edition). Addison-Wesley Professional, Readings, Massachusetts, 2013.
[5]
Marc Levoy. Introduction to computer graphics: Raterization algorithm. http://graphics.stanford.edu/courses/cs248-08/scan/scan1.html, Autumn Quarter 2008. Lecture notes.
[6]
Kevin Weiler and Peter Antherton. Hidden surface removal using polygon area sorting. In Proc. of SPIE 5992, volume 11, pages 214--222, New York, NY, 1977.

Cited By

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  • (2020)Intelligent Building System for 3D Construction of Complex Brick ModelsIEEE Access10.1109/ACCESS.2020.30278078(182506-182516)Online publication date: 2020
  • (2017)MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning LayoutsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.268559436:7(1075-1088)Online publication date: Jul-2017

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  1. An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT

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    cover image ACM Conferences
    DAC '15: Proceedings of the 52nd Annual Design Automation Conference
    June 2015
    1204 pages
    ISBN:9781450335201
    DOI:10.1145/2744769
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 07 June 2015

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    Author Tags

    1. inverse lithography technology (ILT)
    2. look-up table (LUT)
    3. rasterization

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    DAC '15: The 52nd Annual Design Automation Conference 2015
    June 7 - 11, 2015
    California, San Francisco

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    View all
    • (2020)Intelligent Building System for 3D Construction of Complex Brick ModelsIEEE Access10.1109/ACCESS.2020.30278078(182506-182516)Online publication date: 2020
    • (2017)MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning LayoutsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.268559436:7(1075-1088)Online publication date: Jul-2017

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