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Validating SystemC Implementations Against Their Formal Specifications

Authors:

Rolf DrechslerAuthors Info & Claims

SBCCI '14: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

Article No.: 13, Pages 1 - 8

https://doi.org/10.1145/2660540.2660981

Published: 01 September 2014 Publication History

Abstract

The ever increasing complexity of embedded systems leads to a constant strive for higher levels of abstraction. While the design at the Electronic System Level (ESL) with SystemC as the common programming language is state-of-the-art today, also the use of formal specifications by means of modeling languages such as UML or SysML receives more and more attention. This raises the question of how to validate an ESL implementation against a given formal specification. For this, SystemC's limited introspection and reflection features pose a serious obstacle. In this paper, a methodology is presented that retrieves the necessary static and dynamic information which is needed in order to validate a SystemC design. For this purpose, we retrieve information from the SystemC API and compiler-generated debug symbols. The proposed solution can be applied to a wide variety of project setups and requires only minimal adjustments to retrieve the necessary information.

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Digital Library

Cited By

Goli MStoppe JDrechsler R(2020)Automated Nonintrusive Analysis of Electronic System Level DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288966539:2(492-505)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2889665
Przigoda NWille RPrzigoda JDrechsler RPrzigoda NWille RPrzigoda JDrechsler R(2018)Re-utilizing Verification Results of UML/OCL ModelsAutomated Validation & Verification of UML/OCL Models Using Satisfiability Solvers10.1007/978-3-319-72814-8_8(201-233)Online publication date: 17-Jan-2018
https://doi.org/10.1007/978-3-319-72814-8_8
Przigoda NWille RPrzigoda JDrechsler RPrzigoda NWille RPrzigoda JDrechsler R(2018)A Symbolic Formulation for ModelsAutomated Validation & Verification of UML/OCL Models Using Satisfiability Solvers10.1007/978-3-319-72814-8_3(25-94)Online publication date: 17-Jan-2018
https://doi.org/10.1007/978-3-319-72814-8_3
Show More Cited By

Index Terms

Validating SystemC Implementations Against Their Formal Specifications
1. Hardware

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Published In

cover image ACM Conferences

SBCCI '14: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

September 2014

286 pages

ISBN:9781450331562

DOI:10.1145/2660540

Conference Chairs:
Edward David,
Moreno Ordonez,
Program Chairs:
Rodolfo Jardim de Azevedo,
Peter Kinget

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IEEE ICAS
SBC: Brazilian Computer Society
IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
SBMICRO: Brazilian Microelectronics Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2014

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SBCCI '14

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SBC
SIGDA
SBMICRO

SBCCI '14: 27th Symposium on Integrated Circuits and Systems Design

September 1 - 5, 2014

Aracaju, Brazil

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SBCCI '14 Paper Acceptance Rate 40 of 130 submissions, 31%;

Overall Acceptance Rate 133 of 347 submissions, 38%

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Citations

Cited By

Goli MStoppe JDrechsler R(2020)Automated Nonintrusive Analysis of Electronic System Level DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288966539:2(492-505)Online publication date: Mar-2020
https://doi.org/10.1109/TCAD.2018.2889665
Przigoda NWille RPrzigoda JDrechsler RPrzigoda NWille RPrzigoda JDrechsler R(2018)Re-utilizing Verification Results of UML/OCL ModelsAutomated Validation & Verification of UML/OCL Models Using Satisfiability Solvers10.1007/978-3-319-72814-8_8(201-233)Online publication date: 17-Jan-2018
https://doi.org/10.1007/978-3-319-72814-8_8
Przigoda NWille RPrzigoda JDrechsler RPrzigoda NWille RPrzigoda JDrechsler R(2018)A Symbolic Formulation for ModelsAutomated Validation & Verification of UML/OCL Models Using Satisfiability Solvers10.1007/978-3-319-72814-8_3(25-94)Online publication date: 17-Jan-2018
https://doi.org/10.1007/978-3-319-72814-8_3
Goli MStoppe JDrechsler R(2017)Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specificationsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130531(630-633)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130531
Goli MStoppe JDrechsler R(2017)Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specificationsDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927064(630-633)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927064
Gonzalez-de-Aledo PPrzigoda NWille RDrechsler RSanchez P(2017)Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal SpecificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261149436:3(475-488)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2611494
Drechsler RStoppe J(2016)Hardware/Software Co-Visualization on the Electronic System Level Using SystemCProceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2016.45(44-49)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1109/VLSID.2016.45
Drechsler RAutexier SLüth C(2016)Model-Based Specification and Refinement for Cyber-Physical SystemsDynamics in Logistics10.1007/978-3-319-45117-6_1(3-17)Online publication date: 15-Sep-2016
https://doi.org/10.1007/978-3-319-45117-6_1
Przigoda NStoppe JSeiter JWille RDrechsler R(2015)Verification-Driven Design Across Abstraction LevelsProceedings of the 2015 Euromicro Conference on Digital System Design10.1109/DSD.2015.88(375-382)Online publication date: 26-Aug-2015
https://dl.acm.org/doi/10.1109/DSD.2015.88

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