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Reachability Analysis for Formal Verification of SystemC

Published: 04 September 2002 Publication History

Abstract

With ever increasing design sizes, verification becomes the bottleneck in modern design flows. Up to 80% of the overall costs are due to the verification task. Formal methods have been proposed to overcome the limitations of simulation approaches. But these techniques have mainly been applied to lower levels of abstraction. With more and more design complexity the need for hardware description languages with a high level of abstraction becomes obvious.We present a formal verification approach for circuits described in SystemC, an extension of C that allows the modeling of hardware. An algorithm for reachability analysis is proposed and a case study of a scalable bus arbiter cell is given.

Cited By

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  • (2014)Validating SystemC Implementations Against Their Formal SpecificationsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2660981(1-8)Online publication date: 1-Sep-2014
  • (2011)SysfierACM Transactions on Embedded Computing Systems10.1145/1880050.188005510:2(1-35)Online publication date: 7-Jan-2011
  • (2010)A framework for verification of software with time and probabilitiesProceedings of the 8th international conference on Formal modeling and analysis of timed systems10.5555/1885174.1885178(25-45)Online publication date: 8-Sep-2010
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Published In

cover image Guide Proceedings
DSD '02: Proceedings of the Euromicro Symposium on Digital Systems Design
September 2002
ISBN:0769517900

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 September 2002

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Cited By

View all
  • (2014)Validating SystemC Implementations Against Their Formal SpecificationsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2660981(1-8)Online publication date: 1-Sep-2014
  • (2011)SysfierACM Transactions on Embedded Computing Systems10.1145/1880050.188005510:2(1-35)Online publication date: 7-Jan-2011
  • (2010)A framework for verification of software with time and probabilitiesProceedings of the 8th international conference on Formal modeling and analysis of timed systems10.5555/1885174.1885178(25-45)Online publication date: 8-Sep-2010
  • (2009)Verification of an industrial systemC/TLM model using LOTOS and CADPProceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign10.5555/1715759.1715765(46-55)Online publication date: 13-Jul-2009
  • (2008)A temporal language for SystemCProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517446(1-9)Online publication date: 17-Nov-2008
  • (2008)A Comparison of Two SystemC/TLM Semantics for Formal VerificationProceedings of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2008.4547687(59-68)Online publication date: 1-Jun-2008
  • (2007)Formal techniques for SystemC verificationProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278527(188-192)Online publication date: 4-Jun-2007
  • (2004)Checkers for SystemC designsProceedings of the Second ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2004.1459851(171-178)Online publication date: 1-Jan-2004

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