A parallel/serial trade-off methodology for look-up table based decoders

A methodology for architecture exploration of look-up tablebased decoders is presented. For the degree of parallel processinga trade-off can be made by exploring system leveland register transfer level models. Executable specifications(pure functional software models, VHDL behavior models)are used to analyze the performance of different architectures.Hardware cost (area) and feasibility (timing) aredetermined by synthesis of RTL models. These models aregenerated directly out of the specification to avoid errorsdue to manual transformations and to reduce overall designtime. Generator-based reuse modeling and hardware costestimation is demonstrated using a decoder for MPEG variablelength codes (VLC).