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MIS: A Multiple-Level Logic Optimization System

Published: 01 November 2006 Publication History

Abstract

MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.

Cited By

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  • (2023)Heuristic Logic Resynthesis Algorithms at the Core of Peephole OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325634142:11(3958-3971)Online publication date: 1-Nov-2023
  • (2021)Structuring Rule Sets Using Binary Decision DiagramsRules and Reasoning10.1007/978-3-030-91167-6_4(48-61)Online publication date: 8-Sep-2021
  • (2020)A logic synthesis toolbox for reducing the multiplicative complexity in logic networksProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408481(568-573)Online publication date: 9-Mar-2020
  • Show More Cited By

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 6, Issue 6
November 2006
200 pages

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IEEE Press

Publication History

Published: 01 November 2006

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Cited By

View all
  • (2023)Heuristic Logic Resynthesis Algorithms at the Core of Peephole OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325634142:11(3958-3971)Online publication date: 1-Nov-2023
  • (2021)Structuring Rule Sets Using Binary Decision DiagramsRules and Reasoning10.1007/978-3-030-91167-6_4(48-61)Online publication date: 8-Sep-2021
  • (2020)A logic synthesis toolbox for reducing the multiplicative complexity in logic networksProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408481(568-573)Online publication date: 9-Mar-2020
  • (2019)Basic and Advanced Researches in Logic Synthesis and their Industrial ContributionsProceedings of the 2019 International Symposium on Physical Design10.1145/3299902.3311069(109-116)Online publication date: 4-Apr-2019
  • (2018)Folded Circuit SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/322908223:5(1-21)Online publication date: 22-Aug-2018
  • (2017)A Novel Graphical Technique for Combinational Logic Representation and OptimizationComplexity10.1155/2017/96963422017Online publication date: 31-Dec-2017
  • (2016)An efficient method for multi-level approximate logic synthesis under error rate constraintProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897982(1-6)Online publication date: 5-Jun-2016
  • (2016)MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD ToolIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244867535:1(114-127)Online publication date: 1-Jan-2016
  • (2015)Boolean logic optimization in majority-inverter graphsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744806(1-6)Online publication date: 7-Jun-2015
  • (2014)Generating multiple correlated probabilities for MUX-based stochastic computing architectureProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691469(519-526)Online publication date: 3-Nov-2014
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