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Cited By

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Bacis MBuonanno GFerrandi FFummi FGerli LSciuto D(1997)Application of a testing framework to VHDL descriptions at different abstraction levelsProceedings International Conference on Computer Design VLSI in Computers and Processors10.1109/ICCD.1997.628935(654-659)Online publication date: 1997
https://doi.org/10.1109/ICCD.1997.628935
Macii EPoncino MFerrandi FFummi FSciuto DSymonds GNebel W(1996)BDD-based testability estimation of VHDL designsProceedings of the conference on European design automation10.5555/252471.252545(444-449)Online publication date: 20-Sep-1996
https://dl.acm.org/doi/10.5555/252471.252545
Bevacqua RFerrandi FFummi FGuerrazzi L(1996)Implicit test sequences compaction for decreasing test application costProceedings International Conference on Computer Design. VLSI in Computers and Processors10.1109/ICCD.1996.563583(384-389)Online publication date: 1996
https://doi.org/10.1109/ICCD.1996.563583
Show More Cited By

Index Terms

Symbolic optimization of FSM networks based on sequential ATPG techniques
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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The research reported in this paper was conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation (ATPG) algorithms, which can lead to extremely high test generation times. The ...

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

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Published: 01 June 1996

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Bacis MBuonanno GFerrandi FFummi FGerli LSciuto D(1997)Application of a testing framework to VHDL descriptions at different abstraction levelsProceedings International Conference on Computer Design VLSI in Computers and Processors10.1109/ICCD.1997.628935(654-659)Online publication date: 1997
https://doi.org/10.1109/ICCD.1997.628935
Macii EPoncino MFerrandi FFummi FSciuto DSymonds GNebel W(1996)BDD-based testability estimation of VHDL designsProceedings of the conference on European design automation10.5555/252471.252545(444-449)Online publication date: 20-Sep-1996
https://dl.acm.org/doi/10.5555/252471.252545
Bevacqua RFerrandi FFummi FGuerrazzi L(1996)Implicit test sequences compaction for decreasing test application costProceedings International Conference on Computer Design. VLSI in Computers and Processors10.1109/ICCD.1996.563583(384-389)Online publication date: 1996
https://doi.org/10.1109/ICCD.1996.563583
Ferrandi FFummi FMacii EPoncino MSciuto D(1996)BDD-based testability estimation of VHDL designsProceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition10.1109/EURDAC.1996.558241(444-449)Online publication date: 1996
https://doi.org/10.1109/EURDAC.1996.558241
Bevacqua RGuerrazzi LFummi F(1995)SCAN/BIST techniques for decreasing test storage and their implications to test pattern generationProceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies10.1109/EURMIC.1996.546458(351-358)Online publication date: 1995
https://doi.org/10.1109/EURMIC.1996.546458

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Multi-level logic optimization of FSM networks

Improving topological ATPG with symbolic techniques

Complexity of sequential ATPG