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Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design

Authors:

Jason Cong,

Yean-Yow HwangAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 726 - 729

https://doi.org/10.1145/240518.240656

Published: 01 June 1996 Publication History

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References

[1]

Chen, K. C., J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar, "DAG-Map: Graph-based FPGA Technology Mapping for Delay Optimization," IEEE Design and Test of Computers, pp. 7-20, Sep. 1992.

Digital Library

Google Scholar

[2]

Cong, J. and Y. Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," IEEE Trans. on Computer-Aided Design, Vol. 13, pp. 1-12, Jan. 1994.

Digital Library

Google Scholar

[3]

Cong, J. and Y.-Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping," Proc. ACM 3rd Int'l Symp. on FPGA, pp. 68-74, Feb. 1995.

Digital Library

Google Scholar

[4]

Cong, J. and Y.-Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA," in UCLA Computer Science Dept. Tech. Report CSD-950045, (December 1995).

Google Scholar

[5]

Cong, J., J. Peck, and Y. Ding, "RASP: A General Logic Synthesis System for SRAM-based FPGAs," Proc. ACM 4th Int'l Symp. on FPGA, Feb. 1996.

Digital Library

Google Scholar

[6]

Francis, R. J., J. Rose, and Z. Vranesic, "Technology Mapping of Lookup Table-Based FPGAs for Performance," Proc. IEEE Int'l Conf. on CAD, pp. 568-571, Nov. 1991.

Google Scholar

[7]

Garey, M. and D. Johnson, Computer and Intractability: A Guide to the Theory of NP-Completeness, Freeman, San Francisco (1979).

Digital Library

Google Scholar

[8]

Horowitz, E. and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, Potomac, Maryland (1978).

Digital Library

Google Scholar

[9]

Sawkar, P. and D. Thomas, "Performance Directed Technology Mapping for Look-Up Table Based FPGAs," Proc. 30th ACM/IEEE Design Automation Conf., pp. 208- 212, June 1993.

Digital Library

Google Scholar

[10]

Sentovich, E., K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephen, R. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," U.C.Berkeley Technical Report UCB/ERL M92/41, May, 1992.

Google Scholar

Cited By

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Legl CEckl KWurth B(2005)Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play?Field-Programmable Logic Smart Applications, New Paradigms and Compilers10.1007/3-540-61730-2_2(14-23)Online publication date: 6-Jun-2005
https://doi.org/10.1007/3-540-61730-2_2
Chen GCong JHauck S(2001)Simultaneous logic decomposition with technology mapping in FPGA designsProceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays10.1145/360276.360298(48-55)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1145/360276.360298
Cong JHuang HYuan XTrimberger SHauck S(2000)Technology mapping for k/m-macrocell based FPGAsProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329179(51-59)Online publication date: 1-Feb-2000
https://dl.acm.org/doi/10.1145/329166.329179
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Index Terms

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
2. Theory of computation
  1. Computational complexity and cryptography
    1. Complexity classes

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ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

Modern commercial Field-Programmable Gate Array (FPGA) architectures support dual-output look-up tables (LUTs). If the number of total inputs in two small LUTs do not exceed the constraint, e.g., 5 in Xilinx UltraScale+ series, we can pack them into one ...
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

In this paper we study structural gate decomposition in general, simple gate networks for depth-optimal technology mapping using K-input Lookup-Tables (K-LUTs). We show that (1) structural gate decomposition in any K-bounded network results in an ...

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

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DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Legl CEckl KWurth B(2005)Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play?Field-Programmable Logic Smart Applications, New Paradigms and Compilers10.1007/3-540-61730-2_2(14-23)Online publication date: 6-Jun-2005
https://doi.org/10.1007/3-540-61730-2_2
Chen GCong JHauck S(2001)Simultaneous logic decomposition with technology mapping in FPGA designsProceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays10.1145/360276.360298(48-55)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1145/360276.360298
Cong JHuang HYuan XTrimberger SHauck S(2000)Technology mapping for k/m-macrocell based FPGAsProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329179(51-59)Online publication date: 1-Feb-2000
https://dl.acm.org/doi/10.1145/329166.329179
Cong JWu CYoffa EDe Micheli GRabaey J(1997)FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuitsProceedings of the 34th annual Design Automation Conference10.1145/266021.266309(644-649)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266309

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Complexity issues and algorithms for LUT-based FPGA technology mapping

Dual-output LUT merging during FPGA technology mapping

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs