More Web Proxy on the site http://driver.im/

research-article

Cell transformations and physical design techniques for 3D monolithic integrated circuits

Authors:

Shashikanth Bobba,

Ashutosh Chakraborty,

Olivier Thomas,

Perrine Batude,

Giovanni de MicheliAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 9, Issue 3

Article No.: 19, Pages 1 - 28

https://doi.org/10.1145/2491675

Published: 08 October 2013 Publication History

Abstract

3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique, cell-on-cell stacking, and a physical design technique (CELONCEL_PD) aimed at placing cells transformed with cell-on-cell stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.

References

[1]

Batude, P., Vinet, M., Pouydebasque, A., Clavelier, L., Previtali, B., et al. 2008a. Enabling 3D monolithic integration. In Proceedings of the Electro-Chemical Society Spring Meeting (ECS'08). Vol. 16, 47.

[2]

Batude, P., Jaud, M.-A., Thomas, O., Clavelier, L., Pouydebasque, A., et al. 2008b. 3d cmos integration: Introduction of dynamic coupling and application to compact and robust 4t sram. In Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology and Tutorial (ICICDT'08). 281--284.

[3]

Batude, P., Vinet, M., Pouydebasque, A., Le Royer, C., Previtali, B., et al. 2009a. Advances in 3d cmos sequential integration. In Proceedings of the IEEE International Electronic Devices Meeting (IEDM'09). 1--4.

[4]

Batude, P., Vinet, M., Pouydebasque, A., Le Royer, C., Previtali, B., et al. 2009b. GeOI and soi 3d monolithic cell integrations for high density applications. In Proceedings of the Symposium on VLSI Technology. 166--167.

[5]

Batude, P., Vinet, M., Xu, C., Previtali, B., Tabone, C., et al. 2011. Demonstration of low temperature 3d sequential fdsoi integration down to 50nm gate length. In Proceedings of the IEEE Symposium on VLSI Technology. 158--159.

[6]

Bobba, S., Chakraborty, A., Thomas, O., Batude, P., Pavlidis, V. F., and de Micheli, G. 2010. Performance analysis of 3D monolithic integrated circuits. In Proceedings of the IEEE International 3D Systems Integration Conference (3DIC'10). 1--4.

[7]

Bobba, S., Chakraborty, A., Thomas, O., Batude, P., Ernst, T., et al. 2011. CELONCEL: Effective design technique for 3d monolithic integration targeting high performance integrated circuits. In Proceedings of the 16^th Asia and South Pacific Design Automation Conference (ASP-DAC'11). 336--343.

Digital Library

[8]

Chakraborty, A., Kumar, A., and Pan, D. Z. 2009. Regplace: A high quality open-source placement framework for structured asics. In Proceedings of the 46^th ACM/IEEE Design Automation Conference (DAC'09). 442--447.

Digital Library

[9]

Chan, T. F., Cong, J., Shinnerl, J. R., Sze, K., and Xie, M. 2006. MPL6: Enhanced multilevel mixed-size placement. In Proceedings of the International Symposium on Physical Design (ISPD'06). ACM Press, New York, 212--214.

Digital Library

[10]

Cong, J., Luo, G., Wei, J., and Zhang, Y. 2007. Thermal-aware 3d ic placement via transformation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'07). IEEE Computer Society, Washington, DC, 780--785.

[11]

Das, S., Chandrakasan, A., and Reif, R. 2003. Design tools for 3d integrated circuits. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'03). 53--56.

Digital Library

[12]

Deng, Y. and Maly, W. P. 2001. Interconnect characteristics of 2.5-D system integration scheme. In Proceedings of the International Symposium on Physical Design (ISPD'01). ACM Press, New York, 171--175.

Digital Library

[13]

Encounter. 2013. SOC encounter tool. http://www.cadence.com/products/di/soc_encounter/pages/default.aspx.

[14]

Gurobi. 2013. Gurobi optimization. http://www.gurobi.com/.

[15]

Havemann, R. H. and Hutchby, J. A. 2001. High-performance interconnects: An integration overview. Proc. IEEE 89, 5, 586--601.

[16]

Ieong, M., Guarini, K. W., Chan, V., Bernstein, K., Joshi, R., Kedzierski, J., and Haensch, W. 2003. Three dimensional cmos devices and integrated circuits. In Proceedings of the IEEE Custom Integrated Circuits Conference. 207--213.

[17]

ITC99. 1999. http://www.cerc.utexas.edu/itc99-benchmarks/bendoc1.html.

[18]

Itrs. 2009. www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables.

[19]

Jiang, Z.-W., Cheny, T.-C., Hsuy, T.-C., Chenz, H.-C., and Changyz, Y.-W. 2006. Ntuplace2: A hybrid placer using partitioning and analytical techniques. In Proceedings of the International Symposium on Physical Design (ISPD'06). 215--217.

Digital Library

[20]

Jung, S.-M, Jang, J., Cho, W., Moon, J., Kwak, K., et al. 2004. The revolutionary and truly 3-dimensional 25f2 sram technology with the smallest s3 (stacked single-crystal si) cell, 0.16um2, and sstft (stacked single-crystal thin film transistor) for ultra high density sram. In Proceedings of the Symposium on VLSI Technology, Digest of Technical Papers. 228--229.

[21]

Jung, S.-M., Lim, H., Yeo, C., Kwak, K., Son, B., et al. 2007. High speed and highly cost effective 72m bit density s3 sram technology with doubly stacked si layers, peripheral only cosix layers and tungsten shunt w/l scheme for standalone and embedded memory. In Proceedings of the Symposium on VLSI Technology. 68--69. http://toc.proceedings.com/02217webtoc.pdf.

[22]

Kim, H. S., Xue, L., Kumar, A., and Tiwari, S. 2002. Fabrication and electrical properties of buried tungsten structure for direct three dimensional integration. In Proceedings of the International Conference on Solid State Device and Materials (SSDM'02).

[23]

Kim, D. H., Athikulwongse, K., and Lim, S. K. 2009. A study of through-silicon-via impact on the 3d stacked ic layout. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers (ICCAD'09). 674--680.

Digital Library

[24]

Koester, S. J., Young, A. M., Yu, R. R., Purushothaman, S., Chen, K.-N., La Tulipe, D. C., Rana, N., Shi, L., Wordeman, M. R., and Sprogis, E. J. 2008. Wafer-level 3d integration technology. IBM J. Res. Devel. 52, 6, 583--597.

Digital Library

[25]

Lin, M., El-Gamal, A., Lu, Y.-C., and Wong, S. 2007. Performance benefits of monolithically stacked 3d fpga. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 26, 2, 216--229.

Digital Library

[26]

Loh, G. H., Xie, Y., and Black, B. 2007. Processor design in 3d die-stacking technologies. IEEE Micro 27, 3, 31--48.

Digital Library

[27]

Mentor. 2013. Calibre xrc. http://www.mentor.com/products/ic_nanometer_design/verification-signoff/circuit-verification/calibre-xrc/.

[28]

Mit. 2013. 3D Design Kits, version 3DEM.

[29]

Nangate. 2013. 45nm library. http://www.nangate.com/.

[30]

Opencores. 2013. www.opencores.org.

[31]

Pavlidis, V. and Friedman, E. 2009. Three-Dimensional Integrated Circuit Design. Morgan Kaufmann.

Digital Library

[32]

Roy, J. A., Papa, D. A., Adya, S. N., Chan, H. H., Ng, A. N., Lu, J. F., and Markov, I. L. 2005. Capo: Robust and scalable open-source min-cut floorplacer. In Proceedings of the International Symposium on Physical Design (ISPD'05).

Digital Library

[33]

Saraswat, K. C. 2010. 3-D ics: Motivation, performance analysis, technology and applications. In Proceedings of the 17^th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA'10). 1--6.

[34]

Sdc. 2013. Synopsys design compiler. http://www.synopsys.com/home.aspx.

[35]

Sillon, N., Astier, A., Boutry, H., Di Cioccio, L., Henry, D., and Leduc, P. 2008. Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ics. In Proceedings of the IEEE International Electron Devices Meeting (IEDM'08). 1--4.

[36]

Son, Y.-H., Lee, J.-W., Kang, P., Kang, M.-G., Kim, J.- B., et al. 2007. Laser induced epitaxial growth (leg) technology for high density 3d stacked memory with high productivity. In Proceedings of the IEEE Symposium on VLSI Technology, Digest of Technical Papers. 80--81.

[37]

Tezzaron. 2013. Wafer stack with super contacts. http://www.tezzaron.com/about/PhotoAlbum/Products/Wafer_Pair_Super-Contacts.html.

[38]

Wong, S., El-Gamal, A., Griffin, P., Nishi, Y., Pease, F., and Plummer, J. 2007. Monolithic 3d integrated circuits. In Proceedings of the International Symposium on VLSI Technology, Systems and Applications. 1--4.

[39]

Yang, X., Wang, M., Kastner, R., Ghiasi, S., and Sarrafzadeh, M. 2003. Congestion reduction during placement with provably good approximation bound. ACM Trans. Des. Autom. Electron. Syst. 8, 3, 316--333.

Digital Library

[40]

Zhou, L., Wakayama, C., and Shi, C.-J. R 2006. CASCADE: A standard super-cell design methodology with congestion-driven placement for three-dimensional interconnect-heavy very large scale integrated circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 26, 7, 1270--1282.

Digital Library

Cited By

Do CKim CChung S(2023)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04878-6
Chen FSong LLi HChen Y(2021)Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474208(1240-1245)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474208
Chatterjee AMusavvir SKim RDoppa JPande P(2021)Power Management of Monolithic 3D Manycore Chips with Inter-tier Process VariationsACM Journal on Emerging Technologies in Computing Systems10.1145/343076517:2(1-19)Online publication date: 6-Jan-2021
https://dl.acm.org/doi/10.1145/3430765
Show More Cited By

Index Terms

Cell transformations and physical design techniques for 3D monolithic integrated circuits
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits

Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not ...
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of ...
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs
ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and Design

In this paper, we develop physical design tools and methodologies to tackle the inter-tier performance variations caused by low temperature manufacturing in 2-tier gate-level monolithic 3D ICs (M3D). First, we model the top tier front-end-of-line (FEOL) ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 9, Issue 3

September 2013

196 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/2533711

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 08 October 2013

Accepted: 01 June 2012

Revised: 01 May 2012

Received: 01 October 2011

Published in JETC Volume 9, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

Seventh Framework Programme
ST-IBM-LETI alliance program

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
263
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Do CKim CChung S(2023)Aggressive GPU cache bypassing with monolithic 3D-based NoCThe Journal of Supercomputing10.1007/s11227-022-04878-679:5(5421-5442)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04878-6
Chen FSong LLi HChen Y(2021)Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474208(1240-1245)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474208
Chatterjee AMusavvir SKim RDoppa JPande P(2021)Power Management of Monolithic 3D Manycore Chips with Inter-tier Process VariationsACM Journal on Emerging Technologies in Computing Systems10.1145/343076517:2(1-19)Online publication date: 6-Jan-2021
https://dl.acm.org/doi/10.1145/3430765
Guler AJha N(2020)McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.300272328:10(2146-2156)Online publication date: Oct-2020
https://doi.org/10.1109/TVLSI.2020.3002723
Lee DDas SDoppa JPande PChakrabarty K(2019)Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on ChipACM Transactions on Design Automation of Electronic Systems10.1145/335715824:6(1-22)Online publication date: 17-Sep-2019
https://dl.acm.org/doi/10.1145/3357158
Ahn TPerumal RLim SYu Y(2019)Parameter Extraction and Power/Performance Analysis of Monolithic 3-D Inverter (M3INV)IEEE Transactions on Electron Devices10.1109/TED.2018.288581766:2(1006-1011)Online publication date: Feb-2019
https://doi.org/10.1109/TED.2018.2885817
Guler AJha N(2018)Hybrid Monolithic 3-D IC FloorplannerIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.283260726:10(1868-1880)Online publication date: Oct-2018
https://doi.org/10.1109/TVLSI.2018.2832607
Yu YPanth SLim S(2016)Electrical Coupling of Monolithic 3-D InvertersIEEE Transactions on Electron Devices10.1109/TED.2016.2578946(1-4)Online publication date: 2016
https://doi.org/10.1109/TED.2016.2578946
Or-Bach Z(2015)Monolithic 3D IntegrationCHIPS 2020 VOL. 210.1007/978-3-319-22093-2_3(51-91)Online publication date: 20-Sep-2015
https://doi.org/10.1007/978-3-319-22093-2_3

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents