More Web Proxy on the site http://driver.im/

research-article

On the Evolution of Hardware Circuits via Reconfigurable Architectures

Authors:

Davide B. Bartolini,

Matteo Carminati,

Donatella Sciuto,

Marco D. SantambrogioAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 5, Issue 4

Article No.: 22, Pages 1 - 22

https://doi.org/10.1145/2392616.2392620

Published: 01 December 2012 Publication History

Abstract

Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed---the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature.

FPGA-based approaches have emerged as the main architectural solution to implement EHW systems. Various EHW systems have been proposed by researchers but most of them, being based on outdated chips, do not take advantage of the interesting features introduced in newer FPGAs. This article describes a project named Hardware Evolution over Reconfigurable Architectures (HERA), which aims at creating a complete and performance-oriented framework for the evolution of digital circuits, leveraging the reconfiguration technology available in FPGAs. The project is described from its birth to its current state, presenting its evolutionary technique tailored for FPGA-based circuits and the most recent enhancements to improve the scalability with respect to problem size. The developed EHW system outperforms the state of the art, proving its effectiveness in evolving both standard benchmarks and more complex real-world applications.

Supplementary Material

PDF File (a22-cancare_appendix.pdf)

The proof is given in an electronic appendix, available online in the ACM Digital Library.

Download
371.97 KB

References

[1]

Bartolini, D., Cancare, F., Carminati, M., and Sciuto, D. 2011. Hera: Hardware evolution over reconfigurable architectures. In Proceedings of the 1st International Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-Oriented Environments (CHANGE). 1--8.

Digital Library

[2]

Cancare, F., Castagna, M., Renesto, M., and Sciuto, D. 2010a. A highly parallel FPGA-based evolvable hardware architecture. Advances Para. Comput. 19. 608--615.

[3]

Cancare, F., Santambrogio, M., and Sciuto, D. 2010b. A direct bitstream manipulation approach for Virtex4-based evolvable systems. In Proceedings of the IEEE International Symposium on Circuits and Systems. 853--856.

[4]

Claus, C., Ahmed, R., Altenried, F., and Stechele, W. 2010. Towards rapid dynamic partial reconfiguration in video-based driver assistance systems. In Reconfigurable Computing: Architectures, Tools and Applications, Vol. 5992, Springer, Berlin, 55--67.

Digital Library

[5]

Compton, K. and Hauck, S. 2002. Reconfigurable computing: A survey of systems and software. ACM Comput. Surv. 34, 171--210.

Digital Library

[6]

Czerniak, J. and Zarzycki, H. 2002. Application of rough sets in the presumptive diagnosis of urinary system diseases. In Proceedings of the 9th International Conference on Artifical Inteligence and Security in Computing Systems. 41--51.

Digital Library

[7]

de Garis, H. 1993. Evolvable hardware genetic programming of a Darwin machine. In Artificial Neural Nets and Genetic Algorithms, Springer Verlag, 441--449.

[8]

Fogel, D. B. 2006. Evolutionary Computation: Toward a New Philosophy of Machine Intelligence. Wiley-IEEE Press.

Digital Library

[9]

Frank, A. and Asuncion, A. 2011. UCI machine learning repository. www.ics.uci.edu/~mlearn/.

[10]

Glette, K., Torresen, J., and Hovin, M. 2009. Intermediate level FPGA reconfiguration for an online EHW pattern recognition system. In Proceedings of the 4th NASA/ESA Conference on Adaptive Hardware and Systems(HAS). 19--26.

Digital Library

[11]

Glette, K., Torresen, J., Yasunaga, M., and Yamaguchi, Y. 2006. On-chip evolution using a soft processor core applied to image recognition. In Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems (HAS). 373--380.

Digital Library

[12]

Goldberg, D. E. 1989. Genetic Algorithms in Search, Optimization and Machine Learning 1st Ed. Addison-Wesley Longman Publishing Co., Inc., Boston, MA.

Digital Library

[13]

Gordon, T. and Bentley, P. 2005. Development brings scalability to hardware evolution. In Proceedings of the 7th NASA/DoD Conference on Evolvable Hardware. 272--279.

Digital Library

[14]

Greenwood, G. W. and Tyrrell, A. M. 2006. Introduction to Evolvable Hardware: A Practical Guide for Designing Self-Adaptive Systems. Wiley-IEEE Press.

Digital Library

[15]

Higuchi, T., Niwa, T., Tanaka, T., Iba, H., De Garis, H., and Furuya, T. 1993. Evolving hardware with genetic learning: A first step towards building a Darwin machine. In Proceedings of the 2nd International Conference on From Animals to Animats. 417--424.

Digital Library

[16]

Hollingworth, G., Smith, S., and Tyrrell, A. 2000. Safe intrinsic evolution of Virtex devices. In Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware. 195--202.

Digital Library

[17]

Hsiung, P.-A., Santambrogio, M. D., and Huang, C.-H. 2009. Reconfigurable System Design and Verification. CRC Press, Inc.

Digital Library

[18]

Hübner, M. and Becker, J. 2006. Exploiting dynamic and partial reconfiguration for FPGAs: Toolflow, architecture and system integration. In Proceedings of the 19th annual Symposium on Integrated Circuits and Systems Design. 1--4.

Digital Library

[19]

Huelsbergen, L., Rietman, E., and Slous, R. 1999. Evolving oscillators in Silico. IEEE Trans. Evol. Comput. 3, 3, 197--204.

Digital Library

[20]

Irfan, M., Habib, Q., Hassan, G., Yahya, K., and Hayat, S. 2010. Combinational digital circuit synthesis using Cartesian genetic programming from a NAND gate template. In Proceedings of the 6th International Conference on Emerging Technologies. 343--347.

[21]

Kalganova, T. 2000. Bidirectional incremental evolution in extrinsic evolvable hardware. In Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware. 65--74.

Digital Library

[22]

Kalganova, T. and Miller, J. 1999. Evolving more efficient digital circuits by allowing circuit layout Evolution and Multi-objective Fitness. In Proceedings of the 1st NASA/DoD Workshop on Evolvable Hardware. 54--63.

Digital Library

[23]

Lambert, C., Kalganova, T., and Stomeo, E. 2009. FPGA-based systems for evolvable hardware. Intern. J. Elect. Comput. Syst. Eng. 3, 1, 62--68.

[24]

Layzell, P. 1998. The ‘Evolvable Motherboard’. A test pfor the research of intrinsic hardware evolution. Cognitive Science Research Paper 479.

[25]

Levi, D. and Guccione, S. A. 1999. GeneticFPGA: Evolving stable circuits on mainstream FPGA devices. In Proceedings of the 1st NASA/DoD Workshop on Evolvable Hardware. 12--17.

Digital Library

[26]

Li, J., Dong, G., Ramamohanarao, K., and Wong, L. 2004. DeEPs: A new instance-based lazy discovery and classification system. Mach. Learn. 54, 99--124.

Digital Library

[27]

Liu, M., Kuehn, W., Lu, Z., and Jantsch, A. 2009. Run-time partial reconfiguration speed investigation and architectural design space exploration. In Proceedings of the 19th Field Programmable Logic and Applications Conference. 498--502.

[28]

Micheli, G. D. 1994. Synthesis and Optimization of Digital Circuits, 1st Ed. McGraw-Hill Higher Education.

Digital Library

[29]

Miller, J. F., Kalganova, T., Job, D., and Lipnitskaya, N. 2002. The Genetic Algorithm as a Discovery Engine: Strange Circuits and New Principles. Morgan Kaufmann Publishers Inc., 443--466.

[30]

Miller, J. F. and Thomson, P. 1998. Aspects of digital evolution: Evolvability and architecture. In Proceedings of the 5th International Conference on Parallel Problem Solving from Nature. 927--936.

Digital Library

[31]

Montone, A., Santambrogio, M. D., Sciuto, D., and Memik, S. O. 2010. Placement and floorplanning in dynamically reconfigurable FPGAs. ACM Trans. Reconfigur. Technol. Syst. 3, 24, 1--34.

Digital Library

[32]

Olukotun, K. and Hammond, L. 2005. The future of microprocessors. Queue 3, 26--29.

Digital Library

[33]

Oreifej, R., Al-Haddad, R., Tan, H., and Demara, R. 2007. Layered approach to intrinsic evolvable hardware using direct bitstream manipulation of Virtex II Pro devices. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications. 299--304.

[34]

Oza, N. C. and Russell, S. 2001. Experimental comparisons of online and batch versions of bagging and boosting. In Proceedings of the 7th International Conference on Knowledge Discovery and Data Mining. 359--364.

Digital Library

[35]

Papadimitriou, K., Anyfantis, A., and Dollas, A. 2010. An effective framework to evaluate dynamic partial reconfiguration in FPGA systems. IEEE Trans. Instrum. Meas. 59, 6, 1642--1651.

[36]

Patterson, C. and Guccione, S. A. 2001. JBits design abstractions. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. 251--252.

Digital Library

[37]

Porter, R. B. and Bergmann, N. W. 1998. Evolving FPGA based cellular automata. In Proceedings of the 2nd Asia-Pacific Conference on Simulated Evolution and Learning. 114--121.

Digital Library

[38]

Schuck, C., Kuhnle, M., Hubner, M., and Becker, J. 2008. A framework for dynamic 2D placement on FPGAs. In Proceedings of the IEEE International Symposium on Parallel and Distributed Processing. 1--7.

[39]

Sekanina, L. 2007. Evolutionary functional recovery in virtual reconfigurable circuits. J. Emerg. Technol. Comput. Syst. 3, 2. Article 8.

Digital Library

[40]

Sekanina, L. and Friedl, S. 2004. An evolvable combinational unit for FPGAs. Comput. Inform. 23, 5, 461--486.

[41]

Simen Gimle Hansen, D. K. and Torresen, J. 2011. High speed partial run time reconfiguration using enhanced ICAP hard macro. In Proceedings of the 25th International Parallel and Distributed Processing Symposium. 169--175.

[42]

Stomeo, E., Kalganova, T., and Lambert, C. 2006. Generalized disjunction decomposition for evolvable hardware. IEEE Trans. Syst., Man, Cybern. B, Cybern. 36, 5, 1024--1043.

Digital Library

[43]

Terry, M. A., Marcus, J., Farrell, M., Aggarwal, V., and O’Reilly, U.-M. 2006. GRACE: Generative robust analog circuit exploration. In Proceedings of the EvoWorkshops, Vol. 3907, 332--343.

Digital Library

[44]

Thompson, A. 1996. An evolved circuit, intrinsic in silicon, entwined with physics. In Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware. 390--405.

Digital Library

[45]

Thompson, A. 1998. On the automatic design of robust electronics through artificial evolution. In Proceedings of the 2nd International Conference on Evolvable Systems: From Biology to Hardware. 13--24.

Digital Library

[46]

Thompson, A., Layzell, P., and Zebulum, R. 1999. Explorations in design space: Unconventional electronics design through artificial evolution. IEEE Trans. Evol. Comput. 3, 3, 167--196.

Digital Library

[47]

Torresen, J. 1999. Increased complexity evolution applied to evolvable hardware. In Proceedings of Smart Engineering System Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Data Mining, and Complex Systems. 429--436.

[48]

Torresen, J. 2004. An evolvable hardware tutorial. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications. 821--830.

[49]

Tyrrell, A., Hollingworth, G., and Smith, S. 2001. Evolutionary strategies and intrinsic fault tolerance. In Proceedings of the 3rd NASA/DoD Workshop on Evolvable Hardware. 98--106.

Digital Library

[50]

Upegui, A. and Sanchez, E. 2005. Evolving hardware by dynamically reconfiguring Xilinx FPGAs. In Proceedings of the 8th International Conference on Evolvable Systems: From Biology to Hardware. Vol. 3637, 56--65.

Digital Library

[51]

Upegui, A. and Sanchez, E. 2006. Evolving hardware with self-reconfigurable connectivity in Xilinx FPGAs. In Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. 153--162.

Digital Library

[52]

Upegui, A. and Sanchez, E. 2008. Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann, Chapter Evolvable FPGAs, 725--752.

[53]

Upegui, A., Thoma, Y., Sanchez, E., Perez-Uribe, A., Moreno, J. M., and Madrenas, J. 2007. The Perplexus bio-inspired reconfigurable circuit. In Proceedings of the 2nd NASA/ESA Conference on Adaptive Hardware and Systems. 600--605.

Digital Library

[54]

Vasicek, Z., Bidlo, M., Sekanina, L., and Glette, K. 2011. Evolutionary design of efficient and robust switching image filters. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS). 192--199.

[55]

Vasicek, Z. and Sekanina, L. 2007. Evaluation of a new platform for image filter evolution. In Proceedings of the 2nd NASA/ESA Conference on Adaptive Hardware and Systems. 577--586.

Digital Library

[56]

Vasicek, Z., Sekanina, L., and Bidlo, M. 2010. A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations. In Proceedings of Design, Automation Test in Europe Conference Exhibition. 1731--1736.

Digital Library

[57]

Vernekar, D. B., Malhotra, G., and Colaco, V. 2010. Reconfigurable FPGA using genetic algorithm. In Proceedings of the International Conference and Workshop on Emerging Trends in Technology. 493--497.

Digital Library

[58]

Wang, J., Piao, C. H., and Lee, C. H. 2007. Implementing multi-VRC cores to evolve combinational logic circuits in parallel. In Proceedings of the 7th International Conference on Evolvable Systems: From Biology to Hardware. 23--34.

Digital Library

[59]

Williams, J. and Bergmann, N. 2004. Embedded linux as a platform for dynamically self-reconfiguring systems-on-chip. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. 163--169.

[60]

Xilinx Inc. 2006a. ML403 Evaluation Platform User Guide. Xilinx Inc.

[61]

Xilinx Inc. 2006b. OPB HWICAP (v1.00.b) User Guide. Xilinx Inc.

[62]

Xilinx Inc. 2007. Virtex-5 User Guide. Xilinx Inc.

[63]

Xilinx Inc. 2008. Virtex-4 User Guide. Xilinx Inc.

[64]

Xilinx Inc. 2009. Virtex-4 Configuration User Guide. Xilinx Inc.

[65]

Xilinx Inc. 2011. LogiCORE IP XPS HWICAP. Xilinx Inc.

[66]

Yao, X. and Higuchi, T. 1999. Promises and challenges of evolvable hardware. IEEE Trans. Syst., Man, Cybern., C. Appl. Rev. 29, 1, 87--97.

Digital Library

[67]

Yasunaga, M., Yoshihara, I., and Kim, J. H. 2003. Gene finding using evolvable reasoning hardware. In Proceedings of the 5th International Conference on Evolvable Systems: from Biology to Hardware. 198--207.

Digital Library

[68]

Zebulum, R. S., Mojarradi, M., Stoica, A., Keymeulen, D., and Daud, T. 2007. Self-reconfigurable analog arrays: Off-the shelf adaptive electronics for space applications. In Proceedings of the 2nd NASA/ESA Conference on Adaptive Hardware and Systems (AHS). 529--536.

Digital Library

Cited By

Sakali RSk N(2024)Fault-tolerant multiplier using self-healing techniqueMicroelectronics Reliability10.1016/j.microrel.2024.115458160(115458)Online publication date: Sep-2024
https://doi.org/10.1016/j.microrel.2024.115458
Kumar Sakali RMahammad Shak N(2023)Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction AlgorithmJournal of Electronic Testing: Theory and Applications10.1007/s10836-023-06050-139:1(111-122)Online publication date: 29-Mar-2023
https://dl.acm.org/doi/10.1007/s10836-023-06050-1
Šipoš MŠimoňák S(2021)Development of ATmega 328P micro-controller emulator for educational purposesActa Universitatis Sapientiae, Informatica10.2478/ausi-2020-001012:2(159-182)Online publication date: 29-Jan-2021
https://doi.org/10.2478/ausi-2020-0010
Show More Cited By

Index Terms

On the Evolution of Hardware Circuits via Reconfigurable Architectures
1. Hardware
  1. Integrated circuits
    1. Logic circuits

Recommendations

Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems
ISMVL '00: Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments on selected applications, and presents a perspective on the development of ...
Accelerating the evolution of a systolic array-based evolvable hardware system

Evolvable hardware is a type of hardware that is able to adapt to different problems by going through a previous training stage which uses an evolutionary algorithm to find an optimized configuration. This configuration can be achieved through dynamic ...
Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips
Special issue on low power electronics and design

Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-oriented ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 5, Issue 4

December 2012

95 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2392616

Issue’s Table of Contents

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 2012

Accepted: 01 June 2012

Received: 01 March 2012

Published in TRETS Volume 5, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

26
Total Citations
View Citations
582
Total Downloads

Downloads (Last 12 months)9
Downloads (Last 6 weeks)1

Reflects downloads up to 14 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Sakali RSk N(2024)Fault-tolerant multiplier using self-healing techniqueMicroelectronics Reliability10.1016/j.microrel.2024.115458160(115458)Online publication date: Sep-2024
https://doi.org/10.1016/j.microrel.2024.115458
Kumar Sakali RMahammad Shak N(2023)Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction AlgorithmJournal of Electronic Testing: Theory and Applications10.1007/s10836-023-06050-139:1(111-122)Online publication date: 29-Mar-2023
https://dl.acm.org/doi/10.1007/s10836-023-06050-1
Šipoš MŠimoňák S(2021)Development of ATmega 328P micro-controller emulator for educational purposesActa Universitatis Sapientiae, Informatica10.2478/ausi-2020-001012:2(159-182)Online publication date: 29-Jan-2021
https://doi.org/10.2478/ausi-2020-0010
C M(2019)Hardware evolution of AES algorithm on FPGA2019 Innovations in Power and Advanced Computing Technologies (i-PACT)10.1109/i-PACT44901.2019.8960105(1-5)Online publication date: Mar-2019
https://doi.org/10.1109/i-PACT44901.2019.8960105
C M(2019)Improving overall parallelism in AES accelerator using BRAM and multiple input blocks2019 Innovations in Power and Advanced Computing Technologies (i-PACT)10.1109/i-PACT44901.2019.8960016(1-5)Online publication date: Mar-2019
https://doi.org/10.1109/i-PACT44901.2019.8960016
Mora JSalvador RTorre E(2019)On the scalability of evolvable hardware architecturesGenetic Programming and Evolvable Machines10.1007/s10710-018-9340-520:2(155-186)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10710-018-9340-5
YAO RZHU PDU JWANG MZHOU Z(2018)A General Low-Cost Fast Hybrid Reconfiguration Architecture for FPGA-Based Self-Adaptive SystemIEICE Transactions on Information and Systems10.1587/transinf.2017EDP7231E101.D:3(616-626)Online publication date: 2018
https://doi.org/10.1587/transinf.2017EDP7231
Garnica OGlette KTorresen J(2018)Comparing three online evolvable hardware implementations of a classification systemGenetic Programming and Evolvable Machines10.1007/s10710-017-9312-119:1-2(211-234)Online publication date: 1-Jun-2018
https://dl.acm.org/doi/10.1007/s10710-017-9312-1
Sahoo DBag APatranabis SMukhopadhyay DChakraborty R(2018)Fault-Tolerant Implementations of Physically Unclonable Functions on FPGASecurity and Fault Tolerance in Internet of Things10.1007/978-3-030-02807-7_7(129-153)Online publication date: 14-Dec-2018
https://doi.org/10.1007/978-3-030-02807-7_7
Sahoo DPatranabis SMukhopadhyay DChakraborty R(2016)Fault Tolerant Implementations of Delay-Based Physically Unclonable Functions on FPGA2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)10.1109/FDTC.2016.10(87-101)Online publication date: Aug-2016
https://doi.org/10.1109/FDTC.2016.10
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents