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Performance evaluation of the PowerPC 620 microarchitecture

Published: 01 May 1995 Publication History

Abstract

The PowerPC 620™ microprocessor is the most recent and performance leading member of the PowerPC™ family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch prediction scheme, dynamic renaming for all the register files, distributed multi-entry reservation stations, true out-of-order execution by six execution units, and a completion buffer for ensuring precise exceptions. This paper presents an instruction-level performance evaluation of the 620 microarchitecture. A performance simulator is developed using the VMW (Visualization-based Microarchitecture Workbench) retargetable framework. The VMW-based simulator accurately models the microarchitecture down to the machine cycle level. Extensive trace-driven simulation is performed using the SPEC92 benchmarks. Detailed quantitative analyses of the effectiveness of all key microarchitecture features are presented.

References

[1]
R. Colwell and R. Steck. "A 0.61am BiCMOS Processor with Dynamic Execution." ISSCC Proc., 1995.
[2]
T. Diep. "VMW: A Visualization-based Microarchitecture Workbench." Ph.D. Thesis. Carnegie Mellon University, June, 1995.
[3]
L. Gwennap. "Comparing RISC Microprocessors." Proc. of the Microprocessor Forum, Oct. 1994.
[4]
L. Gwennap. "Intel's P6 Uses Decoupled Superscalar Design." Microprocessor Report, February, 1995.
[5]
J. Hennessy and D. Patterson. Computer Architecture." A Quantitative Approach. 1990
[6]
W. Hwu and Y. Patt. "Checkpoint Repair for High-Performance Out-of-Order Execution Machines." IEEETC, Dec. 1987.
[7]
R. Jain. The Art of Computer Systems Performance Analysis, John Wiley & Sons, 1991.
[8]
M. Johnson. Superscalar Microprocessor Design, Prentice-Hall, 1990.
[9]
N. Jouppi. "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance." IEEETC, Dec. 1989.
[10]
D. Kroft. "L,ockup-Free Instruction Fetch/Prefetch Cache Organization. Proc. oflSCA, 1981.
[11]
J. Lee and A. Smith. "Branch Prediction Strategies and Branch Target Buffer Design." Computer, Jan. 1984.
[12]
D. Levita.~. Thomas, and E Tu. "The PowerPC 620 Microprocessor, : A High Performance Superscalar RISC Microprocessor. 'Spring CompCon Proc., 1995.
[13]
E Rubinfeld;,"An Overview of the Alpha AXP 21164 Microarchitecture. Proc. of Hot Chips VI, Oct. 1994.
[14]
R. Tomasulo. "An Efficient Algorithm for Exploiting Multiple Arithmetic Units." IBM JRD, Jan. 1967.
[15]
T. Yeh and Y. Patt. "A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History." Proc. of ISCA, 1993.
[16]
IBM Assembler Language Reference Manual, 1990.
[17]
Motorola Optimizing C and Fortran Compilation System User's Manual, 1992.
[18]
PowerPC 601 RISC Microprocessor User's Manual, 1993.
[19]
PowerPC 603 Microprocessor Implementation Definition, Book IV, 1992.
[20]
PowerPC 604 Microprocessor Implementation Features Book IV, 1993.
[21]
PowerPC 620 Microprocessor Implementation Definition, 1992.
[22]
PowerPC Implementation Definition for the 601 Processor, Book IV, May, 1992
[23]
RS/6000 Special Issue of the IBM JRD, Jan. 1990.
[24]
PowerPC User Instruction Set Architecture, Book I, November 1993
[25]
SPEC Newsletter. Systems Performance Evaluatmn Cooperative, 1992.

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cover image ACM Conferences
ISCA '95: Proceedings of the 22nd annual international symposium on Computer architecture
July 1995
426 pages
ISBN:0897916980
DOI:10.1145/223982
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 23, Issue 2
    Special Issue: Proceedings of the 22nd annual international symposium on Computer architecture (ISCA '95)
    May 1995
    412 pages
    ISSN:0163-5964
    DOI:10.1145/225830
    Issue’s Table of Contents
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Published: 01 May 1995

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ISCA95: International Conference on Computer Architecture
June 22 - 24, 1995
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