Advances in 3D integrated circuits
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- Advances in 3D integrated circuits
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Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits
DSD '11: Proceedings of the 2011 14th Euromicro Conference on Digital System DesignShorter interconnects and higher integration are among the benefits that 3D die-stacking is expected to bring to future integrated circuits. However, when stacking power-dissipating dies one on top of the other, the total power density increases ...
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits
ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and designDue to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the ...
TSV stress aware timing analysis with applications to 3D-IC layout optimization
DAC '10: Proceedings of the 47th Design Automation ConferenceAs the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes ...
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