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research-article

Bridging functional heterogeneity in multicore architectures

Published: 18 February 2011 Publication History

Abstract

Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single-threaded performance coupled with high multi-threaded throughput and higher performance-per-watt. A significant portion of the commercial multicore heterogeneous processors are likely to have a common instruction set architecture( ISA). However, due to limited design resources and goals, each core is likely to contain ISA extensions not yet implemented in the other core. Therefore, such heterogeneous processors will have inherent functional asymmetry at the ISA level and face significant software challenges. This paper analyzes the software challenges to the operating system and the application layer software on a heterogeneous system with functional asymmetry, where the ISA of the small and big cores overlaps. We look at the widely deployed Intel® Architecture and propose solutions to the software challenges that arise when a heterogeneous processor is designed around it. We broadly categorize functional asymmetries into those that can be exposed to application software and those that should be handled by system software. While one can argue that new software written should be heterogeneity-aware, it is important that we find ways in which legacy software can extract the best performance from heterogeneous multicore systems.

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Cited By

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  • (2021)Improving multitask performance and energy consumption with partial-ISA multicoresJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.02.007153(1-14)Online publication date: Jul-2021
  • (2020)Tuning the ISA for increased heterogeneous computation in MPSoCsProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408749(1722-1727)Online publication date: 9-Mar-2020
  • (2020)Tuning the ISA for increased heterogeneous computation in MPSoCs2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116547(1722-1727)Online publication date: Mar-2020
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Information

Published In

cover image ACM SIGOPS Operating Systems Review
ACM SIGOPS Operating Systems Review  Volume 45, Issue 1
January 2011
160 pages
ISSN:0163-5980
DOI:10.1145/1945023
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 February 2011
Published in SIGOPS Volume 45, Issue 1

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Author Tags

  1. Intel® architecture
  2. functional heterogeneity
  3. multicore
  4. operating systems
  5. shared asymmetric ISA

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Cited By

View all
  • (2021)Improving multitask performance and energy consumption with partial-ISA multicoresJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.02.007153(1-14)Online publication date: Jul-2021
  • (2020)Tuning the ISA for increased heterogeneous computation in MPSoCsProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408749(1722-1727)Online publication date: 9-Mar-2020
  • (2020)Tuning the ISA for increased heterogeneous computation in MPSoCs2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116547(1722-1727)Online publication date: Mar-2020
  • (2019)Increasing MPSoCs design space with partial-ISA processors2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS46596.2019.8964683(678-681)Online publication date: Nov-2019
  • (2016)Harnessing Energy Efficiency of Heterogeneous-ISA PlatformsACM SIGOPS Operating Systems Review10.1145/2883591.288360549:2(65-69)Online publication date: 20-Jan-2016
  • (2016)A scheduling algorithm in the randomly heterogeneous multi-core processor2016 12th International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery (ICNC-FSKD)10.1109/FSKD.2016.7603512(2140-2146)Online publication date: Aug-2016
  • (2015)Harnessing energy efficiency of heterogeneous-ISA platformsProceedings of the Workshop on Power-Aware Computing and Systems10.1145/2818613.2818747(6-10)Online publication date: 4-Oct-2015
  • (2015)Multiprocessor real-time scheduling with arbitrary processor affinitiesReal-Time Systems10.1007/s11241-014-9205-951:4(440-483)Online publication date: 1-Jul-2015
  • (2014)Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893207(156-163)Online publication date: Jul-2014
  • (2013)Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicoresProceedings of the First International Workshop on Code OptimiSation for MultI and many Cores10.1145/2446920.2446924(1-10)Online publication date: 24-Feb-2013
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