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Generating power-hungry test programs for power-aware validation of pipelined processors

Authors:

Andrea Calimera,

Danilo Ravotto,

Ernesto Sanchez,

Matteo Sonza ReordaAuthors Info & Claims

SBCCI '10: Proceedings of the 23rd symposium on Integrated circuits and system design

Pages 61 - 66

https://doi.org/10.1145/1854153.1854171

Published: 06 September 2010 Publication History

Abstract

As CMOS technology scaled to nanometer regimes (100nm and below) power dissipation and power density have become major design constraints. The power consumed by active devices is converted into heat, which in turn increases the substrate temperature. Working at high temperatures may affect several figures of merit (e.g., frequency and leakage power), as well as the reliability of the entire system. Therefore, considering power consumption during test and design validation procedures has become a testing due for modern SoCs.

While a huge range of techniques focus on low-power test, we consider the other side of the problem: how to maximize the power absorbed by a processor core (while still remaining into legal operations) in order to test the robustness, and/or validate the functionality of the surrounding components, and the core itself, under high power operating conditions. In this paper, we first demonstrate the actual difficulty of assembling power-hungry test programs on pipelined processors. Second, we propose an automated methodology, based on an automatic optimizer, that allows a push-bottom generation of high-power consuming programs under user-defined constraints. The proposed flow is validated using an open-source pipelined processor mapped into an industrial 65nm technology

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Cited By

Aghaee NPeng ZEles P(2015)A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5541-531:5-6(503-523)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1007/s10836-015-5541-5
Bernardi PDe Carvalho MSanchez EReorda MBosio ADilillo LGirard PValka M(2012)Peak Power EstimationProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.58(167-172)Online publication date: 19-Nov-2012
https://dl.acm.org/doi/10.1109/ATS.2012.58
Valka MBosio ADilillo LGirard PPravossoudovitch SVirazel ASanchez EDe Carvalho MReorda M(2011)A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing2011 Sixteenth IEEE European Test Symposium10.1109/ETS.2011.21(153-158)Online publication date: May-2011
https://doi.org/10.1109/ETS.2011.21

Index Terms

Generating power-hungry test programs for power-aware validation of pipelined processors
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image ACM Conferences

SBCCI '10: Proceedings of the 23rd symposium on Integrated circuits and system design

September 2010

228 pages

ISBN:9781450301527

DOI:10.1145/1854153

General Chair:
João Antonio Martino
USP, Brazil
,
Program Chairs:
Guido Araújo
UNICAMP, Brazil
,
Alex Orailoglu
UCSD, USA
,
Publications Chair:
Felipe Klein
UNICAMP, Brazil

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE ICAS
IEEE Circuits and Systems Society
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 September 2010

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SBCCI '10

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SIGDA

SBCCI '10: 23rd Symposium on Integrated Circuits and Systems Design

September 6 - 9, 2010

São Paulo, Brazil

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Cited By

Aghaee NPeng ZEles P(2015)A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5541-531:5-6(503-523)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1007/s10836-015-5541-5
Bernardi PDe Carvalho MSanchez EReorda MBosio ADilillo LGirard PValka M(2012)Peak Power EstimationProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.58(167-172)Online publication date: 19-Nov-2012
https://dl.acm.org/doi/10.1109/ATS.2012.58
Valka MBosio ADilillo LGirard PPravossoudovitch SVirazel ASanchez EDe Carvalho MReorda M(2011)A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing2011 Sixteenth IEEE European Test Symposium10.1109/ETS.2011.21(153-158)Online publication date: May-2011
https://doi.org/10.1109/ETS.2011.21

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