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research-article

Online cache state dumping for processor debug

Authors:

Preeti Ranjan Panda,

M. BalakrishnanAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 358 - 363

https://doi.org/10.1145/1629911.1630007

Published: 26 July 2009 Publication History

Abstract

Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, followed by (ii) dumping out of the processor's internal state into an external logic analyzer for further offline processing. Internal state of the processor is dominated by the L2 cache. During the process of dumping the cache content, the processor's execution is halted so that the state can be faithfully reproduced offline. In order to reduce the duration for which the processor is halted, and indirectly reduce debug time, we propose two Online Cache Dumping strategies, Retransmit Non-dumped Line (RNL) and Dump History Table (DHT), with the objective of transferring the cache contents while the processor is executing, and yet maintaining fidelity of the dumped data. For typical experimental debug scenarios, we observe that the effective dump times are reduced to between 0.01% and 3.5% of the original times. We also employ compression to reduce the cache content transfer time and logic analyzer space. Our experiments indicate an average compression ratio of 59.2%.

References

[1]

A. R. Alameldeen and D. A. Wood, "Adaptive cache compression for high-performance processors," in ISCA, June 2004.

Digital Library

[2]

A. R. Alameldeen and D. A. Wood, "Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches," Tech. Rep. CS-TR-2004-1500, UW Madison, April 2004.

[3]

D. H. Albonesi, "Selective cache ways: On-demand cache resource allocation," in J. Instruction-Level Parallelism, vol. 2, 2000.

[4]

E. Anis and N. Nicolici, "Low cost debug architecture using lossy compression for silicon debug," in DATE, April 2007.

Digital Library

[5]

K. J. Balakrishnan, N. A. Touba, and S. Patil, "Compressing functional tests for microprocessors," in ATS, December 2005.

Digital Library

[6]

D. Burger and T. Austin, "The Simplescalar tool set, version 2.0," Technical Report cs-tr-97-1342, June 1997.

Digital Library

[7]

J. Edler and M. Hill, "Dinero IV Trace-Driven Uniprocessor Cache Simulator." http://www.cs.wisc.edu/markhill/DineroIV/.

[8]

H. Fang, C. Tong, B. Yao, X. Song, and X. Cheng, "CacheCompress: a novel approach for test data compression with cache for IP embedded cores," in ICCAD, November 2007.

Digital Library

[9]

D. Josephson, "The good, the bad, and the ugly of silicon debug", in DAC, June 2008.

Digital Library

[10]

M. Kjelso, M. Gooch, and S. Jones, "Design and Performance of a Main Memory Hardware Data Compressor," in 22nd EUROMICRO, September 1996.

[11]

J.-S. Lee, W.-K. Hong, and S.-D. Kim, "Design and evaluation of a selective compressed memory system," in ICCD, October 1999.

[12]

H. Lekatsas, J. Henkel, and W. Wolf, "A decompression architecture for low power embedded systems," in ICCD, September 2000.

[13]

S.-B. Park and S. Mitra, "IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors", in DAC, June 2008.

Digital Library

[14]

P. Shivakumar and N. Jouppi, "CACTI 3.0: An integrated cache timing, power and area model," WRL Research Rep., August 2001.

[15]

B. Vermeulen, M. Z. Urfianto, and S. K. Goel, "Automatic generation of breakpoint hardware for silicon debug," in DAC, June 2004.

Digital Library

[16]

A. Vishnoi, P. R. Panda, and M. Balakrishnan, "Cache aware compression for processor debug support", in DATE, April 2009.

Digital Library

[17]

I. Wagner and V. Bertacco, "Reversi: Post-silicon validation system for modern microprocessors", in ICCD, October 2008.

[18]

T. A. Welch, "A technique for high-performance data compression," IEEE Computer, vol. 17, June 1984.

Digital Library

[19]

C. Zhang, F. Vahid, J. Yang, and W. A. Najjar, "A way-halting cache for low-energy high-performance systems," TACO, 2(1), March 2005.

Digital Library

[20]

C. Zhang, F. Vahid, and W. A. Najjar, "A highly-configurable cache architecture for embedded systems," in ISCA, June 2003.

Digital Library

Cited By

Tarapore DRoozkhosh SBrzozowski SMancuso R(2022)Observing the Invisible: Live Cache Inspection for High-Performance Embedded SystemsIEEE Transactions on Computers10.1109/TC.2021.306065071:3(559-572)Online publication date: 1-Mar-2022
https://doi.org/10.1109/TC.2021.3060650
Chandran SPanda P(2018)Debug Data Reduction TechniquesPost-Silicon Validation and Debug10.1007/978-3-319-98116-1_11(211-229)Online publication date: 2-Sep-2018
https://doi.org/10.1007/978-3-319-98116-1_11
Chandran SSarangi SPanda P(2016)Area-Aware Cache Update Trackers for Postsilicon ValidationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.248037824:5(1794-1807)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2480378
Show More Cited By

Index Terms

Online cache state dumping for processor debug
1. Hardware

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Published In

cover image ACM Conferences

DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 July 2009

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DAC '09

Sponsor:

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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Tarapore DRoozkhosh SBrzozowski SMancuso R(2022)Observing the Invisible: Live Cache Inspection for High-Performance Embedded SystemsIEEE Transactions on Computers10.1109/TC.2021.306065071:3(559-572)Online publication date: 1-Mar-2022
https://doi.org/10.1109/TC.2021.3060650
Chandran SPanda P(2018)Debug Data Reduction TechniquesPost-Silicon Validation and Debug10.1007/978-3-319-98116-1_11(211-229)Online publication date: 2-Sep-2018
https://doi.org/10.1007/978-3-319-98116-1_11
Chandran SSarangi SPanda P(2016)Area-Aware Cache Update Trackers for Postsilicon ValidationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.248037824:5(1794-1807)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2480378
Abdel-Khalek RBertacco V(2014)Post-silicon platform for the functional diagnosis and debug of networks-on-chipACM Transactions on Embedded Computing Systems10.1145/256793613:3s(1-25)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2567936
Chandran SSarangi SPanda PMacii E(2013)Space sensitive cache dumping for post-silicon validationProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485412(497-502)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485412
Liu XXu Q(2013)On Multiplexed Signal Tracing for Post-Silicon ValidationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.223235032:5(748-759)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1109/TCAD.2012.2232350
Panda PBalakrishnan MVishnoi A(2011)Compressing Cache State for Postsilicon Processor DebugIEEE Transactions on Computers10.1109/TC.2010.12360:4(484-497)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1109/TC.2010.123
Panda PVishnoi ABalakrishnan M(2010)Enhancing post-silicon processor debug with Incremental Cache state Dumping2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip10.1109/VLSISOC.2010.5642623(55-60)Online publication date: Sep-2010
https://doi.org/10.1109/VLSISOC.2010.5642623

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