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Article

A highly configurable cache architecture for embedded systems

Authors:

Chuanjun Zhang,

Walid NajjarAuthors Info & Claims

ISCA '03: Proceedings of the 30th annual international symposium on Computer architecture

Pages 136 - 146

https://doi.org/10.1145/859618.859635

Published: 01 May 2003 Publication History

Abstract

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.

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Cited By

Ribeiro LJacobi RJunior Fda Silva JSilva I(2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789040
Liu SReviriego PLombardi F(2021)Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)IEEE Transactions on Nanotechnology10.1109/TNANO.2020.304211420(1-9)Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1109/TNANO.2020.3042114
Soliman WPriya BReddy DAnusha PReddy D(2021)Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing UtilizationIEEE Sensors Journal10.1109/JSEN.2020.302036221:2(2334-2345)Online publication date: 15-Jan-2021
https://doi.org/10.1109/JSEN.2020.3020362
Show More Cited By

A highly configurable cache architecture for embedded systems
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '03: Proceedings of the 30th annual international symposium on Computer architecture

June 2003

432 pages

ISBN:0769519458

DOI:10.1145/859618

Conference Chair:
Allan Gottlieb
New York University & NEC Laboratories America
,
Program Chair:
Kai Li
Princeton University

ACM SIGARCH Computer Architecture News Volume 31, Issue 2
ISCA 2003
May 2003
422 pages
ISSN:0163-5964
DOI:10.1145/871656
Issue’s Table of Contents

Copyright © 2003 Authors.

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2003

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ISCA03

Sponsor:

SIGARCH

ISCA03: International Symposium on Computer Architecture

June 9 - 11, 2003

California, San Diego

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ISCA '03 Paper Acceptance Rate 36 of 184 submissions, 20%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

Ribeiro LJacobi RJunior Fda Silva JSilva I(2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789040
Liu SReviriego PLombardi F(2021)Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)IEEE Transactions on Nanotechnology10.1109/TNANO.2020.304211420(1-9)Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1109/TNANO.2020.3042114
Soliman WPriya BReddy DAnusha PReddy D(2021)Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing UtilizationIEEE Sensors Journal10.1109/JSEN.2020.302036221:2(2334-2345)Online publication date: 15-Jan-2021
https://doi.org/10.1109/JSEN.2020.3020362
Navarro OYudi JHoffmann JHernandez HHübner M(2020)A Machine Learning Methodology for Cache Memory Design Based on Dynamic InstructionsACM Transactions on Embedded Computing Systems10.1145/337692019:2(1-20)Online publication date: 11-Mar-2020
https://dl.acm.org/doi/10.1145/3376920
Kuan KAdegbija T(2020)Energy-Efficient Runtime Adaptable L1 STT-RAM Cache DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291292039:6(1328-1339)Online publication date: Jun-2020
https://doi.org/10.1109/TCAD.2019.2912920
Dai CAdegbija T(2020)CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel AttacksIEEE Consumer Electronics Magazine10.1109/MCE.2019.29562069:3(114-120)Online publication date: 1-May-2020
https://doi.org/10.1109/MCE.2019.2956206
Edun AVazquez RGordon-Ross AStitt G(2019)Dynamic Scheduling on Heterogeneous Multicores2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714804(1685-1690)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8714804
Bandara SKinsy MHong Chang CRührmair UHolcomb DSchaumont P(2019)Adaptive Caches as a Defense Mechanism Against Cache Side-Channel AttacksProceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop10.1145/3338508.3359574(55-64)Online publication date: 15-Nov-2019
https://dl.acm.org/doi/10.1145/3338508.3359574
Bruce BPetke JHarman MBarr E(2019)Approximate Oracles and Synergy in Software Energy Search SpacesIEEE Transactions on Software Engineering10.1109/TSE.2018.282706645:11(1150-1169)Online publication date: 1-Nov-2019
https://doi.org/10.1109/TSE.2018.2827066
Vazquez RGordon-Ross AStitt G(2019)Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2019.8906901(1-7)Online publication date: Oct-2019
https://doi.org/10.1109/NORCHIP.2019.8906901
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