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Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

Authors:

Claude Chappert,

Pascale MazoyerAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 9, Issue 2

Article No.: 14, Pages 1 - 16

https://doi.org/10.1145/1596543.1596548

Published: 29 October 2009 Publication History

Abstract

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.

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Cited By

Chandarana PElbtity MF. DeMara RZand R(2024)MRAM-Based FPGAs: A SurveyComputer Memory and Data Storage10.5772/intechopen.108212Online publication date: 10-Jan-2024
https://doi.org/10.5772/intechopen.108212
Nakabeppu SYamasaki N(2024)A Learning-based Control Scheme for MTJ-based Non-volatile Flip-FlopsIPSJ Transactions on System and LSI Design Methodology10.2197/ipsjtsldm.17.1617(16-35)Online publication date: 2024
https://doi.org/10.2197/ipsjtsldm.17.16
Xu YZhao ZXiao YYu TMulaosmanovic HKleimaier DDuenkel SBeyer SGong XJoshi RHu XWen SRios ALekkala KItti LHoman EGeorge SNarayanan VNi K(2024)Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machinesScience Advances10.1126/sciadv.adk152510:3Online publication date: 19-Jan-2024
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Index Terms

Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 9, Issue 2

October 2009

118 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1596543

Issue’s Table of Contents

Copyright © 2009 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 October 2009

Accepted: 01 February 2009

Revised: 01 December 2008

Received: 01 June 2008

Published in TECS Volume 9, Issue 2

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Cited By

Chandarana PElbtity MF. DeMara RZand R(2024)MRAM-Based FPGAs: A SurveyComputer Memory and Data Storage10.5772/intechopen.108212Online publication date: 10-Jan-2024
https://doi.org/10.5772/intechopen.108212
Nakabeppu SYamasaki N(2024)A Learning-based Control Scheme for MTJ-based Non-volatile Flip-FlopsIPSJ Transactions on System and LSI Design Methodology10.2197/ipsjtsldm.17.1617(16-35)Online publication date: 2024
https://doi.org/10.2197/ipsjtsldm.17.16
Xu YZhao ZXiao YYu TMulaosmanovic HKleimaier DDuenkel SBeyer SGong XJoshi RHu XWen SRios ALekkala KItti LHoman EGeorge SNarayanan VNi K(2024)Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machinesScience Advances10.1126/sciadv.adk152510:3Online publication date: 19-Jan-2024
https://doi.org/10.1126/sciadv.adk1525
Kumar RDivyanshu DKhan DAmara SMassoud Y(2023)Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security ApplicationsElectronics10.3390/electronics1204090212:4(902)Online publication date: 10-Feb-2023
https://doi.org/10.3390/electronics12040902
Morsali MTabrizchi SMarshall ARoohi AMisra DAngizi S(2023)Design and Evaluation of a Near-Sensor Magneto-Electric FET-Based Event DetectorIEEE Transactions on Electron Devices10.1109/TED.2023.329638970:9(4822-4828)Online publication date: Sep-2023
https://doi.org/10.1109/TED.2023.3296389
Rangaprasad SJoshi VKaushik B(2023)A fully non-volatile reconfigurable magnetic decoderMicroelectronics Journal10.1016/j.mejo.2023.105956141:COnline publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1016/j.mejo.2023.105956
Raouf MTimarchi S(2022)Reducing the Effect of Carry Propagation on Spintronic AddersSPIN10.1142/S201032472150032612:01Online publication date: 11-Feb-2022
https://doi.org/10.1142/S2010324721500326
Kim JSong YCho KLee HYoon HChung E(2022)STT-MRAM-Based Multicontext FPGA for Multithreading Computing EnvironmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309144041:5(1330-1343)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3091440
Yu TXu YDeng SZhao ZJao NKim YDuenkel SBeyer SNi KGeorge SNarayanan V(2022)Hardware functional obfuscation with ferroelectric active interconnectsNature Communications10.1038/s41467-022-29795-313:1Online publication date: 25-Apr-2022
https://doi.org/10.1038/s41467-022-29795-3
Zhang ZLuo YCui YYang HZhang QXu GWu ZXiang JLiu QYin HMao SWang XLi JZhang YLuo QGao JXiong WLiu JLi YLi JLuo JWang W(2022)A Polarization-Switching, Charge-Trapping, Modulated Arithmetic Logic Unit for In-Memory Computing Based on Ferroelectric Fin Field-Effect TransistorsACS Applied Materials & Interfaces10.1021/acsami.1c2018914:5(6967-6976)Online publication date: 25-Jan-2022
https://doi.org/10.1021/acsami.1c20189
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