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Physically-aware N-detect test pattern selection

Published: 10 March 2008 Publication History

Abstract

N-detect test has been shown to have a higher likelihood for detecting defects. However, traditional definitions of N-detect test do not necessarily exploit the localized characteristics of defects. In physically-aware N-detect test, the objective is to ensure that the N tests establish N different logical states on the signal lines that are in the physical neighborhood surrounding the targeted fault site. We present a test selection procedure for creating a physically-aware N-detect test set that satisfies a user-provided constraint on test-set size. Results produced for an industrial test chip demonstrate the effectiveness and practicability of our pattern selection approach. Specifically, we show that we can virtually detect the same number of faults 10 or more times as a traditional 10-detect test set and increase the number of neighborhood states and the number of faults with 10 or more states by 18.0 and 4.7%, respectively, without increasing the number of tests over a traditional 10-detect test set.

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Cited By

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  • (2014)Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuitsIET Computers & Digital Techniques10.1049/iet-cdt.2013.00778:2(83-89)Online publication date: Mar-2014
  • (2011)Statistical defect-detection analysis of test sets using readily-available tester dataProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132492(768-773)Online publication date: 7-Nov-2011
  • (2011)A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality ObjectivesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.215769330:11(1767-1772)Online publication date: 1-Nov-2011
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cover image ACM Conferences
DATE '08: Proceedings of the conference on Design, automation and test in Europe
March 2008
1575 pages
ISBN:9783981080131
DOI:10.1145/1403375
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 March 2008

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DATE '08: Design, Automation and Test in Europe
March 10 - 14, 2008
Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2014)Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuitsIET Computers & Digital Techniques10.1049/iet-cdt.2013.00778:2(83-89)Online publication date: Mar-2014
  • (2011)Statistical defect-detection analysis of test sets using readily-available tester dataProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132492(768-773)Online publication date: 7-Nov-2011
  • (2011)A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality ObjectivesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.215769330:11(1767-1772)Online publication date: 1-Nov-2011
  • (2011)Generation of Compact Stuck-At Test Sets Targeting Unmodeled DefectsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.210175030:5(787-791)Online publication date: 1-May-2011
  • (2009)Generation of compact test sets with high defect coverageProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874894(1130-1135)Online publication date: 20-Apr-2009

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