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Optimum test patterns for parity networks

Authors:

D. C. Bossen,

D. L. Ostapko,

A. M. PatelAuthors Info & Claims

AFIPS '70 (Fall): Proceedings of the November 17-19, 1970, fall joint computer conference

Pages 63 - 68

https://doi.org/10.1145/1478462.1478472

Published: 17 November 1970 Publication History

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Abstract

The logic related to the error detecting and/or correcting circuitry of digital computers often contains portions which calculate the parity of a collection of bits. A tree structure composed of Exclusive-OR gates is used to perform this calculation. Similar to any other circuitry, the operation of this parity tree is subject to malfunctions. A procedure for testing malfunctions in a parity tree is presented in this report.

References

[1]

J E MacDonald Design methods for maximum minimum-distance error correcting codes IBM J of R & D Vol 4 pp 43--47 1960

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[2]

W W Peterson Error correcting codes MIT Press Cambridge Massachusetts 1961

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[3]

A M Patel Maximal group codes with specified minimum distance IBM J of R&D Vol 14 pp 434--443 1970

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Jha N(2006)Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.6279910:1(136-143)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.62799
Tarnick S(2006)Controllable self-checking checkers for conditional concurrent checkingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.38441514:5(547-553)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.384415
Hughes J(2006)Multiple fault detection using single fault test setsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.31377:1(100-108)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.3137
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A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks

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Published In

AFIPS '70 (Fall): Proceedings of the November 17-19, 1970, fall joint computer conference

November 1970

683 pages

ISBN:9781450379045

DOI:10.1145/1478462

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 November 1970

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Cited By

View all

Jha N(2006)Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.6279910:1(136-143)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.62799
Tarnick S(2006)Controllable self-checking checkers for conditional concurrent checkingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.38441514:5(547-553)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.384415
Hughes J(2006)Multiple fault detection using single fault test setsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.31377:1(100-108)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.3137
Jone WMadden P(2006)Multiple fault testing using minimal single fault test set for fanout-free circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.18485112:1(149-157)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.184851
Nikolos D(1998)Optimal Self-Testing Embedded Parity CheckersIEEE Transactions on Computers10.1109/12.66016747:3(313-321)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1109/12.660167
Anderson DMetze G(1995)Design of Totally Self-Checking Check Circuits for M-out of-N CodesTwenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'.10.1109/FTCSH.1995.532641(244)Online publication date: 1995
https://doi.org/10.1109/FTCSH.1995.532641
Tarnick S(1994)Controllable self-checking checkers for conditional concurrent checkingProceedings of IEEE VLSI Test Symposium10.1109/VTEST.1994.292321(144-150)Online publication date: 1994
https://doi.org/10.1109/VTEST.1994.292321
Jone WWu C(1994)Multiple Fault Detection in Parity CheckersIEEE Transactions on Computers10.1109/12.31211843:9(1096-1099)Online publication date: 1-Sep-1994
https://dl.acm.org/doi/10.1109/12.312118
Cheng-Juei Wu Wen-Ben Jone (1993)On Multiple Fault Detection Of Parity Checkers1993 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1993.692946(1515-1518)Online publication date: 1993
https://doi.org/10.1109/ISCAS.1993.692946
Wu CJone W(1993)On multiple fault detection of parity checkers1993 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1993.394023(1515-1518)Online publication date: 1993
https://doi.org/10.1109/ISCAS.1993.394023
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A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks

Novel designs of nanometric parity preserving reversible compressor

Design of Parity Testable Combinational Circuits