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Clock gating for power optimization in ASIC design cycle theory & practice

Published: 11 August 2008 Publication History

Abstract

In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design.

Cited By

View all
  • (2018)Detecting non-functional circuit activity in SoC designsProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201720(464-469)Online publication date: 22-Jan-2018
  • (2018)On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing TechniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.281717726:7(1377-1390)Online publication date: 1-Jul-2018
  • (2017)A Survey on Authenticated Encryption--ASIC Designer’s PerspectiveACM Computing Surveys10.1145/313127650:6(1-21)Online publication date: 6-Dec-2017
  • Show More Cited By

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  1. Clock gating for power optimization in ASIC design cycle theory & practice

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      cover image ACM Conferences
      ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design
      August 2008
      396 pages
      ISBN:9781605581095
      DOI:10.1145/1393921
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 August 2008

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      Author Tags

      1. ASIC
      2. RTL
      3. SoC
      4. low power
      5. optimization

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      Overall Acceptance Rate 398 of 1,159 submissions, 34%

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      Cited By

      View all
      • (2018)Detecting non-functional circuit activity in SoC designsProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201720(464-469)Online publication date: 22-Jan-2018
      • (2018)On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing TechniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.281717726:7(1377-1390)Online publication date: 1-Jul-2018
      • (2017)A Survey on Authenticated Encryption--ASIC Designer’s PerspectiveACM Computing Surveys10.1145/313127650:6(1-21)Online publication date: 6-Dec-2017
      • (2015)Clock domain crossing aware sequential clock gatingProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755755(1-6)Online publication date: 9-Mar-2015
      • (2012)PowerAdviserProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492845(550-553)Online publication date: 12-Mar-2012

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