• Thibeault C and Gagnon G. (2018). On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:7. (1377-1390). Online publication date: 1-Jul-2018.

    https://doi.org/10.1109/TVLSI.2018.2817177

  • Peterson D, Boekle Y and Bringmann O. Detecting non-functional circuit activity in SoC designs. Proceedings of the 23rd Asia and South Pacific Design Automation Conference. (464-469).

    /doi/10.5555/3201607.3201720

  • Kavun E, Mihajloska H and Yalçin T. (2017). A Survey on Authenticated Encryption--ASIC Designer’s Perspective. ACM Computing Surveys. 50:6. (1-21). Online publication date: 30-Nov-2018.

    https://doi.org/10.1145/3131276

  • Liu J, Hong M, Do K, Choi J, Park J, Kumar M, Kumar M, Tripathi N and Ranjan A. Clock domain crossing aware sequential clock gating. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition. (1-6).

    /doi/10.5555/2755753.2755755

  • Vyagrheswarudu N, Das S and Ranjan A. PowerAdviser. Proceedings of the Conference on Design, Automation and Test in Europe. (550-553).

    /doi/10.5555/2492708.2492845