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Simultaneous power and thermal integrity driven via stapling in 3D ICs

Published: 05 November 2006 Publication History

Abstract

The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven viastapling in 3D design. The transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. Using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. Experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal vias by on average 11.5%, and simultaneous optimization using transient thermal analysis reduces non-signal vias by on average 34%. The via reduction would be higher for the 3D design with more device layers.

References

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Cited By

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  • (2017)Fast Nonlinear Dynamic Compact Thermal Modeling With Multiple Heat Sources in Ultra-Thin Chip Stacking TechnologyIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2016.26234207:1(58-69)Online publication date: Jan-2017
  • (2014)P/G TSV planning for IR-drop reduction in 3D-ICsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616661(1-6)Online publication date: 24-Mar-2014
  • (2014)Globally Constrained Locally Optimized 3-D Power Delivery NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228380022:10(2131-2144)Online publication date: Oct-2014
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    cover image ACM Conferences
    ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
    November 2006
    147 pages
    ISBN:1595933891
    DOI:10.1145/1233501
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 November 2006

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    Author Tags

    1. structured and parameterized model order reduction
    2. thermal modeling and management

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    View all
    • (2017)Fast Nonlinear Dynamic Compact Thermal Modeling With Multiple Heat Sources in Ultra-Thin Chip Stacking TechnologyIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2016.26234207:1(58-69)Online publication date: Jan-2017
    • (2014)P/G TSV planning for IR-drop reduction in 3D-ICsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616661(1-6)Online publication date: 24-Mar-2014
    • (2014)Globally Constrained Locally Optimized 3-D Power Delivery NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228380022:10(2131-2144)Online publication date: Oct-2014
    • (2013)Benchmarking for research in power delivery networks of three-dimensional integrated circuitsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451922(17-24)Online publication date: 24-Mar-2013
    • (2013)A study of tapered 3-D TSVs for power and thermal integrityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218708121:2(306-319)Online publication date: 1-Feb-2013
    • (2013)Dynamic Electrothermal Macromodeling: an Application to Signal Integrity Analysis in Highly Integrated Electronic SystemsIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2013.22536093:7(1237-1243)Online publication date: Jul-2013
    • (2012)Fast thermal simulations of vertically integrated circuits (3D ICs) including thermal vias13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems10.1109/ITHERM.2012.6231482(588-596)Online publication date: May-2012
    • (2012)The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated Circuits17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6165010(53-58)Online publication date: Jan-2012
    • (2012)A Hierarchical Modeling Approach of Thermal Vias Using CNT-based CompositesBio and Nano Packaging Techniques for Electron Devices10.1007/978-3-642-28522-6_30(601-620)Online publication date: 17-Jul-2012
    • (2011)Power delivery design for 3-D ICs using different through-silicon via (TSV) technologiesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203816519:4(647-658)Online publication date: 1-Apr-2011
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