Utilizing logic information in multi-level timing simulation
Pages 215 - 218
References
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J. Benkoski. Statistical Timing Verification and Delay Fault Detection by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. PhD thesis, Carnegie Mellon University, 1989.
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R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
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R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. Mis: A multiple-level logic optimization system. IEEE Transactions on Computer-Aided Design, CAD-6(6):1062-1081, November 1987.
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F. Brgles and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. In ISCAS85, June 1985.
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J. Carter, V. Iyengar, and B. Rosen. Efficient test coverage determination for delay faults. In IEEE International Test Conference, 1987.
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M.P. Chew. Utilizing Logic Information in Statistical Timing Simulation. PhD thesis, Carnegie Mellon University, 1990.
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K. Cho and R. E. Bryant. Test pattern generation for sequential mos circuits by symbolic fault simulation. In 26th Design Automation Conference, pages 418-23, 1989.
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E.B. Eichelberger. Hazard detection in combinational and sequential switching circuits. IBM Journal of Research and Development 9.90-99, March 1965.
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S. Ghosh. Dynamic multi-level simulation of digital hardware designs. Simulation, 48(6):247-252, 1987.
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R. Lisanke. Logic Synthesis and Optimization Benchmarks User Guide Version 2.0. Microelectronics Center of North Carolina. 1988.
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C. Liu. Elements of Discrete Mathematics. McGraw-Hill Book Company, 1977.
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R. E. Miller. Switching Theory Volume II:Sequential Circuits and Machines. Wiley and Sons, Inc., 1965.
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Index Terms
- Utilizing logic information in multi-level timing simulation
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