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Article

Evaluation of the field-programmable cache: performance and energy consumption

Authors:

Domingo Benitez,

Dolores I. Rexachs,

Emilio LuqueAuthors Info & Claims

CF '06: Proceedings of the 3rd conference on Computing frontiers

Pages 361 - 372

https://doi.org/10.1145/1128022.1128070

Published: 03 May 2006 Publication History

Abstract

Many authors have proposed power management techniques for general-purpose processors at the cost of degraded performance such as lower IPC or longer delay. Some proposals have focused on cache memories because they consume a significant fraction of total microprocessor power. We propose a reconfigurable and adaptive cache microarchitecture based on field-programmable technology that is intended to deliver high performance at low energy consumption. In this paper, we evaluate the performance and energy consumption of a run-time algorithm when used to manage a field-programmable L1 data cache. The adaptation strategy is based on two techniques: a learning process provides the best cache configuration for each program phase, and a recognition process detects program phase changes by using data working-set signatures to activate a low-overhead reconfiguration mechanism. Our proposals achieve performance improvement and cache energy saving at the same time. Considering a design scenario driven by performance constraints, we show that processor execution time and cache energy consumption can be reduced on average by 15.2% and 9.9% compared to a non-adaptive high-performance microarchitecture. Alternatively, when energy saving is prioritized and considering a non-adaptive energy-efficient microarchitecture as baseline, cache energy and processor execution time are reduced on average by 46.7% and 9.4% respectively. In addition to comparing to conventional microarchitectures, we show that the proposed microarchitecture achieves better performance and more cache energy reduction than other configurable caches.

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Cited By

Zang WGordon-Ross A(2013)A survey on cache tuning from a power/energy perspectiveACM Computing Surveys10.1145/2480741.248074945:3(1-49)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2480741.2480749
Tao JHillenbrand DWang LMarten H(2010)Studying Filter Cache Bypassing on Embedded SystemsProceedings of the 2010 10th IEEE International Conference on Computer and Information Technology10.1109/CIT.2010.296(1679-1686)Online publication date: 29-Jun-2010
https://dl.acm.org/doi/10.1109/CIT.2010.296
Tao JHillenbrand DMarten H(2009)Instruction Hints for Super Efficient Data CachesProceedings of the 9th International Conference on Computational Science10.1007/978-3-642-01973-9_76(677-685)Online publication date: 25-May-2009
https://dl.acm.org/doi/10.1007/978-3-642-01973-9_76
Show More Cited By

Index Terms

Evaluation of the field-programmable cache: performance and energy consumption
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

Information

Published In

cover image ACM Conferences

CF '06: Proceedings of the 3rd conference on Computing frontiers

May 2006

430 pages

ISBN:1595933026

DOI:10.1145/1128022

General Chairs:
Monica Alderighi
IASF - INAF
,
Valentina Salapura
IBM
,
Program Chair:
Sally A. McKee
Cornell University

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 May 2006

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CF06: Computing Frontiers Conference

May 3 - 5, 2006

Ischia, Italy

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Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

Zang WGordon-Ross A(2013)A survey on cache tuning from a power/energy perspectiveACM Computing Surveys10.1145/2480741.248074945:3(1-49)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2480741.2480749
Tao JHillenbrand DWang LMarten H(2010)Studying Filter Cache Bypassing on Embedded SystemsProceedings of the 2010 10th IEEE International Conference on Computer and Information Technology10.1109/CIT.2010.296(1679-1686)Online publication date: 29-Jun-2010
https://dl.acm.org/doi/10.1109/CIT.2010.296
Tao JHillenbrand DMarten H(2009)Instruction Hints for Super Efficient Data CachesProceedings of the 9th International Conference on Computational Science10.1007/978-3-642-01973-9_76(677-685)Online publication date: 25-May-2009
https://dl.acm.org/doi/10.1007/978-3-642-01973-9_76
Tao JKunze MKarl W(2008)Evaluating the Cache Architecture of Multicore ProcessorsProceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)10.1109/PDP.2008.22(12-19)Online publication date: 13-Feb-2008
https://dl.acm.org/doi/10.1109/PDP.2008.22
Tao JKunze MNowak FBuchty RKarl W(2008)Performance advantage of reconfigurable cache design on multicore processor systemsInternational Journal of Parallel Programming10.1007/s10766-008-0075-436:3(347-360)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1007/s10766-008-0075-4
Tao JHoàng KKarl W(2007)CMP Cache Architecture and the OpenMP PerformanceProceedings of the 3rd international workshop on OpenMP: A Practical Programming Model for the Multi-Core Era10.1007/978-3-540-69303-1_7(77-88)Online publication date: 3-Jun-2007
https://dl.acm.org/doi/10.1007/978-3-540-69303-1_7

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