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Diagonal routing in high performance microprocessor design

Published: 24 January 2006 Publication History

Abstract

This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan routing with horizontal and vertical directions, a new diagonal routing capability is added as one of the routing functions. With this enhancement, diagonal routing becomes an additional strategy for improving delays of critical paths in the microprocessor design. This method was applied to the prototype chip of the Fujitsu SPARC64 microprocessor with two CPU cores using 90nm process technology. By applying the diagonal routing to long distance nets, net length is reduced by 36% per net on average. When the diagonal routing is applied to a critical path, path delay is improved by as much as about 14 pico-seconds per net on a path. This improvement is more than the delay of a gate with no load. This prototype chip proved that our method was effective in reducing the total net length and improving path delays.

References

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N. Ito, H. Komatsu, et al, "A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor", Proc. ICCD, pp. 204--210, 2003.
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M. Nishihara, T. Murase, et al, "Single-Board CPU Packaging for the FACOM M-780", Fujitsu Scientific and Technical Journal, 23, 4, pp.226--235, 1987.
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Takumi Maruyama, "SPARC64 VI: Fujitsu's Next Generation Processor", presented at the microprocessor forum, 2003.

Cited By

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  • (2011)Single-Layer Trunk Routing Using Minimal 45-Degree LinesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.2510E94-A:12(2510-2518)Online publication date: 2011

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Published In

cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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  1. diagonal routing
  2. manhattan routing
  3. microprocessor

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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  • (2011)Single-Layer Trunk Routing Using Minimal 45-Degree LinesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.2510E94-A:12(2510-2518)Online publication date: 2011

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