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Article

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model

Published: 24 January 2006 Publication History

Abstract

Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDC-Tree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSMT) heuristic algorithm to construct an OARSMT. CDC-Tree is based on the current driven circuit (CDC) model mapped from an escape graph. The circuit structure comes from the topology of the escape graph, with each edge replaced by a resistor indicating the wirelength of that edge. By performing DC analysis on the circuit and selecting the edges according to the current distribution to construct an OARSMT, the wirelength of the resulting tree is short. The algorithm has been implemented and tested on cases of different scales and with different shapes of obstacles. Experiments show that CDCTree can achieve shorter wirelength than the existing best algorithm, An-OARSMan, when the terminal number of a net is less than 50.

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  • (2015)The Global Shortest Path Visualization Approach with ObstructionsJournal of Robotics and Mechatronics10.20965/jrm.2015.p057927:5(579-585)Online publication date: 20-Oct-2015
  • (2014)Global shortest path visualization approach with obstructionsProceedings of the 2014 International Conference on Advanced Mechatronic Systems10.1109/ICAMechS.2014.6911577(393-397)Online publication date: Aug-2014
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Published In

cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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View all
  • (2021)An Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Method Using PB-SATIETE Journal of Research10.1080/03772063.2021.196779069:6(3346-3356)Online publication date: 1-Sep-2021
  • (2015)The Global Shortest Path Visualization Approach with ObstructionsJournal of Robotics and Mechatronics10.20965/jrm.2015.p057927:5(579-585)Online publication date: 20-Oct-2015
  • (2014)Global shortest path visualization approach with obstructionsProceedings of the 2014 International Conference on Advanced Mechatronic Systems10.1109/ICAMechS.2014.6911577(393-397)Online publication date: Aug-2014
  • (2014)Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approachIntegration, the VLSI Journal10.1016/j.vlsi.2013.08.00147:1(105-114)Online publication date: 1-Jan-2014
  • (2011)Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree constructionProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950922(527-532)Online publication date: 25-Jan-2011
  • (2011)Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722246(527-532)Online publication date: Jan-2011
  • (2009)Generation of optimal obstacle-avoiding rectilinear Steiner minimum treeProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687405(21-25)Online publication date: 2-Nov-2009
  • (2009)High-performance obstacle-avoiding rectilinear steiner tree constructionACM Transactions on Design Automation of Electronic Systems10.1145/1529255.152926714:3(1-29)Online publication date: 4-Jun-2009
  • (2009)Global and detailed routingElectronic Design Automation10.1016/B978-0-12-374364-0.50019-9(687-749)Online publication date: 2009
  • (2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
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