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Power phase variation in a commercial server workload

Published: 04 October 2006 Publication History

Abstract

Many techniques have been developed for adaptive power management of computing systems. These techniques rely on the presence of varying power phases to detect opportunities for adaptation. However, little information is available regarding the extent of power phases in real systems. This paper illustrates available power phases ranging from 1 millisecond to 1 second using a commercial workload running on enterprise class hardware. Data is obtained using a server instrumented for power measurement at the subsystem level. The analysis shows that chipset, memory and disk subsystems have the most homogenous phase behavior with greater than 71% of samples within phases of 100 milliseconds or shorter. In contrast, CPU and I/O subsystems have much more variation with only 26% of samples within phases of 10 milliseconds or shorter.

References

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  • (2008)Analysis of dynamic power management on multi-core processorsProceedings of the 22nd annual international conference on Supercomputing10.1145/1375527.1375575(327-338)Online publication date: 7-Jun-2008

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Published In

cover image ACM Conferences
ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design
October 2006
446 pages
ISBN:1595934626
DOI:10.1145/1165573
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 October 2006

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Author Tags

  1. chipset
  2. commercial workload characterization
  3. disk
  4. memory
  5. microprocessor
  6. power
  7. program phase

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ISLPED06
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ISLPED06: International Symposium on Low Power Electronics and Design
October 4 - 6, 2006
Bavaria, Tegernsee, Germany

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all
  • (2008)Analysis of dynamic power management on multi-core processorsProceedings of the 22nd annual international conference on Supercomputing10.1145/1375527.1375575(327-338)Online publication date: 7-Jun-2008

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