Article

Runtime identification of microprocessor energy saving opportunities

Authors:

W. L. Bircher,

M. Valluri,

J. Law,

L. K. JohnAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 275 - 280

https://doi.org/10.1145/1077603.1077668

Published: 08 August 2005 Publication History

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Abstract

High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the solution of these problems by presenting: linear regression models for power consumption and a detailed study of energy efficiency in a modern out-of-order superscalar microprocessor. These simple (2-input) yet accurate (2.6% error) models provide a valuable tool for identifying opportunities to apply power saving techniques such as clock throttling and dynamic voltage scaling (DVS). Also, future work in improving energy efficiency is motivated by a detailed analysis of SPEC CPU 2000 workloads. The vast majority of workloads are found to yield very low energy efficiency due to the frequency of level two (L2) cache misses and misspeculated instructions

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Runtime identification of microprocessor energy saving opportunities
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Information

Published In

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 August 2005

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ISLPED05

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Yue AWilde TMartin SYew PMehta S(2023)ReAPER: Region Aware Power and Energy RegulatorProceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624275(1894-1897)Online publication date: 12-Nov-2023
https://dl.acm.org/doi/10.1145/3624062.3624275
Rapp MAmrouch HLin YYu BPan DWolf MHenkel J(2022)MLCAD: A Survey of Research in Machine Learning for CAD Keynote PaperIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312476241:10(3162-3181)Online publication date: Oct-2022
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Wu HChen CWeng K(2020)Two Designs of Automatic Embedded System Energy Consumption Measuring Platforms Using GPIOApplied Sciences10.3390/app1014486610:14(4866)Online publication date: 16-Jul-2020
https://doi.org/10.3390/app10144866
Gotz MKhriji SCheour RArief WKanoun O(2020)Benchmarking-Based Investigation on Energy Efficiency of Low-Power MicrocontrollersIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2020.298281069:10(7505-7512)Online publication date: Oct-2020
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Chasapis DMoretó MSchulz MRountree BValero MCasas MEigenmann RDing CMcKee S(2019)Power efficient job scheduling by predicting the impact of processor manufacturing variabilityProceedings of the ACM International Conference on Supercomputing10.1145/3330345.3330372(296-307)Online publication date: 26-Jun-2019
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Wu QFlolid SSong SDeng JJohn L(2018)Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU20172018 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2018.8573479(71-77)Online publication date: Sep-2018
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Zheng XVikalo HSong SJohn LGerstlauer A(2017)Sampling-based binary-level cross-platform performance estimationProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130779(1713-1718)Online publication date: 27-Mar-2017
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