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Article

Nanoscale CMOS circuit leakage power reduction by double-gate device

Authors:

Koushik K. Das,

Rajiv V. Joshi,

Ching-Te ChuangAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 102 - 107

https://doi.org/10.1145/1013235.1013267

Published: 09 August 2004 Publication History

Abstract

Leakage power for extremely scaled (Leff = 25 nm) double-gate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that double-gate technology is an ideal candidate for low-power applications. Unique double-gate device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design trade-offs for double-gate CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for double-gate device are analyzed considering state dependency, showing that leakage current is reduced by a factor of over 10X, compared with conventional bulk-Si counterpart.

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Cited By

Pang YZhou YTong LXu J(2023)2D Dual Gate Field‐Effect Transistor Enabled Versatile FunctionsSmall10.1002/smll.20230417320:2Online publication date: 13-Sep-2023
https://doi.org/10.1002/smll.202304173
Bourahla NHadri BBourahla A(2021)Impact of Channel Doping Concentration on the Performance Characteristics and the Reliability of Ultra-Thin Double Gate DG-FinFET Compared with Nano-Single Gate FD-SOI-MOSFET by Using TCAD-Silvaco ToolSilicon10.1007/s12633-021-01121-414:7(3477-3491)Online publication date: 1-May-2021
https://doi.org/10.1007/s12633-021-01121-4
Shi JLi MRahman MKhasanvis SMoritz C(2017)NP-Dynamic Skybridge: A Fine-Grained 3D IC Technology with NP-Dynamic LogicIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2017.26847815:2(286-299)Online publication date: 1-Apr-2017
https://doi.org/10.1109/TETC.2017.2684781
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Index Terms

Nanoscale CMOS circuit leakage power reduction by double-gate device
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information

Published In

cover image ACM Conferences

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 09 August 2004

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ISLPED04

Sponsor:

ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Citations

Cited By

Pang YZhou YTong LXu J(2023)2D Dual Gate Field‐Effect Transistor Enabled Versatile FunctionsSmall10.1002/smll.20230417320:2Online publication date: 13-Sep-2023
https://doi.org/10.1002/smll.202304173
Bourahla NHadri BBourahla A(2021)Impact of Channel Doping Concentration on the Performance Characteristics and the Reliability of Ultra-Thin Double Gate DG-FinFET Compared with Nano-Single Gate FD-SOI-MOSFET by Using TCAD-Silvaco ToolSilicon10.1007/s12633-021-01121-414:7(3477-3491)Online publication date: 1-May-2021
https://doi.org/10.1007/s12633-021-01121-4
Shi JLi MRahman MKhasanvis SMoritz C(2017)NP-Dynamic Skybridge: A Fine-Grained 3D IC Technology with NP-Dynamic LogicIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2017.26847815:2(286-299)Online publication date: 1-Apr-2017
https://doi.org/10.1109/TETC.2017.2684781
Veera Boopathy E Raghul G. Karthick K. (2015)Low power and high performance MOSFET2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)10.1109/VLSI-SATA.2015.7050455(1-5)Online publication date: Jan-2015
https://doi.org/10.1109/VLSI-SATA.2015.7050455
Shi JLi MRahman MKhasanvis SMoritz C(2015)Architecting NP-Dynamic SkybridgeProceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)10.1109/NANOARCH.2015.7180607(169-174)Online publication date: Jul-2015
https://doi.org/10.1109/NANOARCH.2015.7180607
Devi SSingh ALorenzo RChaudhury S(2015)Comparative study of Single Gate And Double Gate Fully Depleted Silicon on Insulator MOSFET2015 Communication, Control and Intelligent Systems (CCIS)10.1109/CCIntelS.2015.7437940(357-362)Online publication date: Nov-2015
https://doi.org/10.1109/CCIntelS.2015.7437940
Singh AHu J(2014)Case studies on variation tolerant and low power design using planar asymmetric double gate transistor2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2014.6908591(1021-1024)Online publication date: Aug-2014
https://doi.org/10.1109/MWSCAS.2014.6908591
Manorama Shrivastava PAkashe S(2013)Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology2013 7th International Conference on Intelligent Systems and Control (ISCO)10.1109/ISCO.2013.6481167(301-306)Online publication date: Jan-2013
https://doi.org/10.1109/ISCO.2013.6481167
Dhar SPattanaik MRajaram P(2011)Advancement in nanoscale CMOS device design en route to ultra-low-power applicationsVLSI Design10.1155/2011/1785162011(1-19)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/178516
Kim KDas KChuang C(2007)High-density data-retention power gating structure using a four-terminal double-gate deviceInternational Journal of Electronics10.1080/0020721070128891894:4(403-412)Online publication date: Apr-2007
https://doi.org/10.1080/00207210701288918
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