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A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs

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Abstract

As the design complexity increases, the attack space for malicious modifications in the design also increases. Attackers in untrusted phases during the Integrated Circuit (IC) design cycle may embed a Hardware Trojan (HT). A potential and stealthy HT is triggered with nets that rarely switch during regular circuit operation. Detection of HT in the host design requires exhaustive simulation to activate the HT during pre- and post-silicon. For analyzing HT vulnerability, we present a modeling approach to capture the rare nets using word-level statistics of the inputs. It provides the capability to locate macro-block(s) in a Register Transfer Level (RTL) design to estimate the rare triggering nets. Given RTL description of a design, we decompose the design into a subset of basic arithmetic modules, each of which is pre-characterized (empirically and analytically) by which we evaluate the design for quick estimation of HT vulnerable macro-block(s). The relative impact of mapping the design to a particular module from its analytical characteristics can be used to detect “low activity” and “local regions” without expensive low-level simulation. We implement the model over a wide range of input signal statistics for Digital Signal Processing (DSP) Intellectual Property (IP) cores, and the average estimation error for different bit-widths and correlations is less than 2%. We also propose cost functions during mapping and show that identification of rare activity blocks (nets) at a higher level is closely related to the simulation results. The final mapping that identifies the candidate arithmetic modules can minimize HT vulnerability in design at the cost of accuracy.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA

    Sheikh Ariful Islam, Love Kumar Sah & Srinivas Katkoori

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  1. Sheikh Ariful Islam
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  2. Love Kumar Sah
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  3. Srinivas Katkoori
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Correspondence to Sheikh Ariful Islam.

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Islam, S.A., Sah, L.K. & Katkoori, S. A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs. J Hardw Syst Secur 4, 246–262 (2020). https://doi.org/10.1007/s41635-020-00100-2

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