[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content
Log in

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

  • Original Research Paper
  • Published:
Journal of Real-Time Image Processing Aims and scope Submit manuscript

Abstract

Embedded Block Coding with Optimized Truncation (EBCOT) used in JPEG2000 standard performs the sequential processing of code blocks for clear images. The employment of Matrix Quantizer (MQ) in EBCOT reduces the computational burden by generating the context decision pair from probabilistic estimation. But, it consumes huge devices and occupies large memory space that leads to the difficulties in hardware design. The bit truncation in MQ-coder reduces the computational complexities that lead to a reduction in the memory space occupation in the hardware platform. This paper proposes the Auxiliary Minutest MQ (AMMQ) architecture for bit truncation in the probability estimation of context decision pair making. The reduction in a number of bits minimizes the slice registers and lookup tables utilization that offers less flip-flop consumption to achieve the compact chip development for JPEG2000 compression. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The comparative analysis of proposed AMMQ-coder architecture with the existing architectures regarding the memory assures the effectiveness of new way of bit truncation scheme in the JPEG2000 compression.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. Taubman, D.: High performance scalable image compression with EBCOT. IEEE Trans. Image Process. 9, 1158–1170 (2000)

    Article  Google Scholar 

  2. Zhang, Y.-Z., Xu, C., Wang, W.-T., Chen, L.-B.: Performance analysis and architecture design for parallel EBCOT encoder of JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 17, 1336–1347 (2007)

    Article  Google Scholar 

  3. Varma, K., Damecharla, H.B., Bell, A.E., Carletta, J.E., Back, G.V.: A fast JPEG2000 encoder that preserves coding efficiency: the split arithmetic encoder. IEEE Trans. Circuits Syst. I Regul. Pap. 55, 3711–3722 (2008)

    Article  MathSciNet  Google Scholar 

  4. Dyer, M., Nooshabadi, S., Taubman, D.: Design and analysis of system on a chip encoder for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 19, 215–225 (2009)

    Article  Google Scholar 

  5. Acharya, T., Tsai, P.-S.: JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures. Wiley, New York (2005)

    Google Scholar 

  6. Mei, K., Zheng, N., Huang, C., Liu, Y., Zeng, Q.: VLSI design of a high-speed and area-efficient JPEG2000 encoder. IEEE Trans. Circuits Syst. Video Technol. 8, 1065–1078 (2007)

    Google Scholar 

  7. Gupta, A.K., Nooshabadi, S., Taubman, D., Dyer, M.: Realizing low-cost high-throughput general-purpose block encoder for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 16, 843–858 (2006)

    Article  Google Scholar 

  8. Yamauchi, H., Okada, S., Taketa, K., Matsuda, Y., Mori, T., Watanabe, T., et al.: 1440 × 1080 pixel, 30 frames per second motion-JPEG2000 codec for HD-movie transmission. IEEE J. Solid-State Circuits 40, 331–341 (2005)

    Article  Google Scholar 

  9. Makhzan, M.A., Khajeh, A., Eltawil, A., Kurdahi, F.J.: A low power JPEG2000 encoder with iterative and fault tolerant error concealment. IEEE Trans. Very Large Scale Integr. VLSI Syst. 17, 827–837 (2009)

    Article  Google Scholar 

  10. Liu, L., Chen, N., Meng, H., Zhang, L., Wang, Z., Chen, H.: A VLSI architecture of JPEG2000 encoder. IEEE J. Solid-State Circuits 39, 2032–2040 (2004)

    Article  Google Scholar 

  11. Horrigue, L., Saidani, T., Ghodhbani, R., Dubois, J., Miteran, J., Atri, M.: An efficient hardware implementation of MQ decoder of the JPEG2000. Microprocess. Microsyst. 38, 659–668 (2014)

    Article  Google Scholar 

  12. Saponara, S., Fanucci, L., Marsi, S., Ramponi, G.: Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing. J. Real-Time Image Proc. 1, 267–283 (2007)

    Article  Google Scholar 

  13. Saponara, S., Fanucci, L., Petri, E.: A multi-processor NoC-based architecture for real-time image/video enhancement. J. Real-Time Image Proc. 8, 111–125 (2013)

    Article  Google Scholar 

  14. Marsi, S., Saponara, S.: Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design. J. Real-Time Image Proc. 5, 275–289 (2010)

    Article  Google Scholar 

  15. Blanes, I., Magli, E., Serra-Sagrista, J.: A tutorial on image compression for optical space imaging systems. IEEE Geosci. Remote Sens. Mag. 2, 8–26 (2014)

    Article  Google Scholar 

  16. Rhu, M., Park, I.-C.: Optimization of arithmetic coding for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 20, 446–451 (2010)

    Article  Google Scholar 

  17. Tuan, H.N., Trang, H.: An efficient pipeline architecture of JPEG2000 MQ-coder”, Tạp chí Khoa họ c và Kỹ thuật - Họ c viện KTQS số 153, 2013

  18. Ahmadvand, M., Ezhdehakosh, A.: A new pipelined architecture for JPEG2000 MQ-coder. In: Proceedings of the World Congress on Engineering and Computer Science, pp. 24–26 (2012)

  19. Deng, C., Lin, W., Lee, B.-S., Lau, C.T.: Robust image coding based upon compressive sensing. IEEE Trans. Multimedia 14, 278–290 (2012)

    Article  Google Scholar 

  20. Sarawadekar, K., Banerjee, S.: VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG2000. VLSI J. Integr. 45, 1–8 (2012)

    Article  Google Scholar 

  21. Lucking, D.J., Balster, E.J., Hill, K.L., Scarpino, F.A.: FPGA implementation of the JPEG2000 binary arithmetic (MQ) decoder. J. Real-Time Image Proc. 8, 411–419 (2013)

    Article  Google Scholar 

  22. Matela, J., Šrom, M., Holub, P.: Low GPU occupancy approach to fast arithmetic coding in JPEG2000. In: Kotásek, Z., Bouda, J., Černá, I., Sekanina, L., Vojnar, T., Antoš, D. (eds.) Mathematical and Engineering Methods in Computer Science, MEMICS 2011. Lecture Notes in Computer Science, vol 7119. Springer, Berlin, Heidelberg

  23. Belyaev, E., Liu, K., Gabbouj, M., Li, Y.: An efficient adaptive binary range coder and its VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. 25, 1435–1446 (2015)

    Article  Google Scholar 

  24. Hsin, H.-C., Sung, T.-Y., Shieh, Y.-S.: A fast MQ table based merging algorithm for image segmentation. In: International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2012 IEEE, pp. 1009–1012 (2012)

  25. Xiang, T., Yu, C., Chen, F.: Secure MQ coder: an efficient way to protect JPEG2000 images in wireless multimedia sensor networks. Sig. Process. Image Commun. 29, 1015–1027 (2014)

    Article  Google Scholar 

  26. De Silva, A.M., Bailey, D.G., Punchihewa, A.: Exploring the implementation of JPEG compression on FPGA. In: 2012 6th International Conference on Signal Processing and Communication Systems (ICSPCS), pp. 1–9 (2012)

  27. Jie, G., YunSong, L., Kai, L., Jie, L., Chengke, W.: Efficient VLSI architecture of JPEG2000 encoder. In: 2013 6th International Congress on Image and Signal Processing (CISP), pp. 192–197 (2013)

  28. Pascual, J.M., Mora, H.M., Guilló, A.F., López, J.A.: Adjustable compression method for still JPEG images. Sig. Process. Image Commun. 32, 16–32 (2015)

    Article  Google Scholar 

  29. Balster, E., Turri, W., Scarpino, F., Walker, D., Marrara, T., Benjamin, Simone, K., Vicen, N., Lucking, D., Mundy, D., Flaherty, M.: Embedded JPEG2000 Compression/Decompression Engines For Real-Time Processing Of Large-Scale Imagery. US Patent US 8,170,333 B2, US 8,170,334 B2, US 8,170,335 B2, University of Dayton, Dayton

  30. Sarkar, P., Indurkar, P., Kadam, R.: An optimum algorithm for data compression using VHDL. Int. Res. J. Eng. Technol. 02, 572–576 (2015)

    Google Scholar 

  31. Sarawadekar, K., Banerjee, S.: An efficient pass-parallel architecture for embedded block coder in JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 21, 825–836 (2011)

    Article  Google Scholar 

  32. Kumar, N.R., Xiang, W., Wang, Y.: Two-symbol FPGA architecture for fast arithmetic encoding in JPEG2000. J. Signal Process. Syst. 69, 213–224 (2012)

    Article  Google Scholar 

  33. Saidani, T., Atri, M., Said, Y., Tourki, R.: Real time FPGA acceleration for discrete wavelet transform of the 5/3 filter for JPEG2000. In: 2012 36th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT), pp. 393–399 (2012)

  34. Saidani, T., Atri, M., Khriji, L., Tourki, R.: An efficient hardware implementation of parallel EBCOT algorithm for JPEG2000. J. Real-Time Image Process. 11, 1–12 (2013)

    Google Scholar 

  35. Inatsuki, T., Matsuura, M., Morinaga, K., Tsutsui, H., Miyanaga, Y.: An FPGA implementation of low-latency video transmission system using lossless and near-lossless line-based compression. In: 2015 IEEE International Conference on Digital Signal Processing (DSP), pp. 1062–1066 (2015)

  36. Liu, K., Zhou, Y., Li, Y.S., Ma, J.F.: A high performance MQ encoder architecture in JPEG2000. VLSI J. Integr. 43, 305–317 (2010)

    Article  Google Scholar 

  37. Kulkarni, O.C., Sarawadekar, K., Banerjee, S.: VLSI implementation of MQ decoder in JPEG2000. In: Students’ Technology Symposium (TechSym), 2011 IEEE, pp. 193–197 (2011)

  38. Descampe, A., Devaux, F.O., Rouvroy, G., Legat, J., Quisquater, J.J., Macq, B.: A flexible hardware JPEG2000 decoder for digital cinema. IEEE Trans. Circuits Syst. Video Technol. 16, 1397–1410 (2006)

    Article  Google Scholar 

  39. Horrigue, L., Saidani, T., Ghodhbane, R., Atri, M.: A high performance MQ decoder architecture in JPEG2000. In: 2014 World Congress on Computer Applications and Information Systems (WCCAIS), pp. 1–5 (2014)

  40. Zezza, S., Masera, G., Nooshabadi, S.: A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic. In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 902–905 (2014)

  41. Emre, Y., Chakrabarti, C.: Techniques for compensating memory errors in JPEG2000. IEEE Trans. Very Large Scale Integr. VLSI Syst. 21, 159–163 (2013)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to S. D. Jayavathi.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Jayavathi, S.D., Shenbagavalli, A. FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000. J Real-Time Image Proc 16, 1765–1779 (2019). https://doi.org/10.1007/s11554-017-0683-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11554-017-0683-6

Keywords

Navigation