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Last level cache size heterogeneity in embedded systems

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Abstract

In typical multicore processors, last level caches are formed by distributed clusters of memory banks of the same size, namely homogeneous ones. By shutting down part of these clusters to save power along generations of multicore processors, clusters with non-homogeneous cache sizes can be originated, named as heterogeneous ones. Given that heterogeneous clusters have typically smaller sizes than the homogeneous ones, they present larger miss rates that are likely to deteriorate performance. In this investigation, we study the impact of heterogeneous caches in embedded microprocessors, by having an arbitrary mix of homogeneous and heterogeneous clusters. That is, we propose to evaluate the architectural implications of these heterogeneous caches and a flexible algorithm that can be used to explore them. From scientific applications’ experimental benchmarking, our findings show that microprocessors with heterogeneous clusters present a maximal performance degradation of about 10 % and maximal performance improvement of 16 %, while obtaining maximum miss hit rate of reduction and improvement up to 10 %. In addition, 10 % of coherence activity decrease when presenting maximum energy utilization up to 50 % and maximum energy reduction of 15 %.

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Acknowledgments

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the funding agencies or institutions. We would like to thank Maria Amelia Guitti and anonymous reviewers for their valuable comments and feedbacks. This research is based upon work partially supported by Ministry of Science and Technology (MOST)/Taiwan and The Providence University research project awards.

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Authors and Affiliations

  1. Leeds Beckett University, Leeds, UK

    Mario D. Marino

  2. Providence University, Taichung, Taiwan

    Kuan-Ching Li

Authors
  1. Mario D. Marino
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  2. Kuan-Ching Li
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Corresponding author

Correspondence to Kuan-Ching Li.

Appendix

Appendix

See Figs. 14, 15, 16, 17 and 18.

Fig. 14
figure 14

Top to bottom a Miss rate, b number of misses, and c writebacks versus L2 size for FFT

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Fig. 15
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Top to bottom a Miss rate, b number of misses, and c writebacks versus L2 size for FMM

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Fig. 16
figure 16

Top to bottom a Miss rate, b number of misses, and c writebacks versus L2 size for LU

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Fig. 17
figure 17

Top to bottom a Miss rate, b number of misses, and c writebacks versus L2 size for Ocean

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Fig. 18
figure 18

Top to bottom a Miss rate, b number of misses, and c writebacks versus L2 size for Water

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Marino, M.D., Li, KC. Last level cache size heterogeneity in embedded systems. J Supercomput 72, 503–544 (2016). https://doi.org/10.1007/s11227-015-1576-8

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