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Improving power efficiency of D-NUCA caches

Authors:

P. StenströmAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 4

Pages 53 - 58

https://doi.org/10.1145/1327312.1327321

Published: 01 September 2007 Publication History

Abstract

D-NUCA caches are cache memories that, thanks to banked organization, broadcast search and promotion/demotion mechanism, are able to tolerate the increasing wire delay effects introduced by technology scaling. As a consequence, they will outperform conventional caches (UCA, Uniform Cache Architectures) in future generation cores.

Due to the promotion/demotion mechanism, we have found that, in a D-NUCA cache, the distribution of hits on the ways varies across applications as well as across different execution phases within a single application. In this paper, we show how such a behavior can be utilized to improve D-NUCA power efficiency as well as to decrease its access latencies. In particular, we propose a new D-NUCA structure, called Way Adaptable D-NUCA cache, in which the number of active (i.e. powered-on) ways is dynamically adapted to the need of the running application. Our initial evaluation shows that a consistent reduction of both the average number of active ways (42% in average) and the number of bank access requests (29% in average) is achieved, without significantly affecting the IPC.

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Cited By

Agarwalla BDas SSahu N(2022)Process variation aware DRAM-Cache resizingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102364123:COnline publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102364
Marino MLi K(2016)Last level cache size heterogeneity in embedded systemsThe Journal of Supercomputing10.1007/s11227-015-1576-872:2(503-544)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1007/s11227-015-1576-8
Wang HLai CHuang YLu SWang RLuan ZQian D(2014)Remapping NUCAProceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)10.1109/HPCC.2014.13(38-41)Online publication date: 20-Aug-2014
https://dl.acm.org/doi/10.1109/HPCC.2014.13
Show More Cited By

Index Terms

Improving power efficiency of D-NUCA caches
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 4

September 2007

59 pages

ISSN:0163-5964

DOI:10.1145/1327312

Issue’s Table of Contents

Copyright © 2007 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2007

Published in SIGARCH Volume 35, Issue 4

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Citations

Cited By

Agarwalla BDas SSahu N(2022)Process variation aware DRAM-Cache resizingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102364123:COnline publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102364
Marino MLi K(2016)Last level cache size heterogeneity in embedded systemsThe Journal of Supercomputing10.1007/s11227-015-1576-872:2(503-544)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1007/s11227-015-1576-8
Wang HLai CHuang YLu SWang RLuan ZQian D(2014)Remapping NUCAProceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)10.1109/HPCC.2014.13(38-41)Online publication date: 20-Aug-2014
https://dl.acm.org/doi/10.1109/HPCC.2014.13
Wang XMa KWang Y(2012)Cache Latency Control for Application Fairness or Differentiation in Power-Constrained Chip MultiprocessorsIEEE Transactions on Computers10.1109/TC.2011.18761:10(1371-1385)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1109/TC.2011.187
Wang XMa KWang Y(2010)Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip MultiprocessorsProceedings of the 2010 39th International Conference on Parallel Processing10.1109/ICPP.2010.9(1-10)Online publication date: 13-Sep-2010
https://dl.acm.org/doi/10.1109/ICPP.2010.9
Kotera IEgawa RTakizawa HKobayashi HFoglia PPrete CBartolini SGiorgi R(2008)Modeling of cache access behavior based on Zipf's lawProceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture10.1145/1509084.1509086(9-15)Online publication date: 26-Oct-2008
https://dl.acm.org/doi/10.1145/1509084.1509086
Bardine AComparetti MFoglia PGabrielli GPrete C(2008)Performance Sensitivity of NUCA Caches to On-Chip Network ParametersProceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing10.1109/SBAC-PAD.2008.20(167-174)Online publication date: 29-Oct-2008
https://dl.acm.org/doi/10.1109/SBAC-PAD.2008.20

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