Abstract
Advances in CMOS technology have made possible the increase of integrated circuit’s density, which impacts directly on the circuit’s performance. However, technology scaling poses some reliability concerns that directly affect the circuit’s lifetime. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits’ paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of Integrated Circuits (ICs) is proposed. In more detail, the technique is based on an on-chip sensor able to monitor IC’s aging and to adjust its power supply voltage in order to minimize NBTI effects and increase the circuit’s lifetime. Experimental results obtained throughout simulations demonstrate the technique’s efficiency, since the circuit’s lifetime has been increased by 150 %. Finally, the analysis of the main overheads introduced as well as the impact related to process variation renders the evaluation of the proposed approach possible.
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This work has been partially funded by FAPERGS/CAPES Edital 014/2012.
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Copetti, T., Cardoso Medeiros, G., Bolzani Poehls, L. et al. NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time. J Electron Test 32, 315–328 (2016). https://doi.org/10.1007/s10836-016-5592-2
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DOI: https://doi.org/10.1007/s10836-016-5592-2