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Ping-Hung Yuh
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2010 – 2019
- 2015
- [c12]Keh-Jeng Chang, Shih-Hao Lee, Kuo-Fu Lee, Ping-Hung Yuh, Ho-Che Yu, Wen-Cheng Huang, Victor C. Y. Chang:
Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes. VLSI-DAT 2015: 1-4 - 2012
- [j8]Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
:
Optimized 3D Network-on-Chip Design Using Simulated Allocation. ACM Trans. Design Autom. Electr. Syst. 17(2): 12:1-12:19 (2012) - 2011
- [c11]Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho
A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7 - 2010
- [c10]Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
Application-specific 3D Network-on-Chip design using simulated allocation. ASP-DAC 2010: 517-522
2000 – 2009
- 2009
- [j7]Ping-Hung Yuh, Sachin S. Sapatnekar
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1295-1306 (2009) - [j6]Ping-Hung Yuh, Chia-Lin Yang
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14(4): 51:1-51:28 (2009) - [j5]Ping-Hung Yuh, Chia-Lin Yang
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 14(4): 52:1-52:26 (2009) - 2008
- [j4]Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1621-1634 (2008) - [j3]Ping-Hung Yuh, Chia-Lin Yang
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1928-1941 (2008) - [c9]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289 - 2007
- [j2]Ping-Hung Yuh, Chia-Lin Yang
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. ACM J. Emerg. Technol. Comput. Syst. 3(3): 13 (2007) - [j1]Ping-Hung Yuh, Chia-Lin Yang
Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): 37 (2007) - [c8]Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu:
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC 2007: 447-452 - [c7]Ping-Hung Yuh, Chia-Lin Yang
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757 - [c6]Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97 - 2006
- [c5]Ping-Hung Yuh, Chia-Lin Yang
Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934 - 2005
- [c4]Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang
A routing algorithm for flip-chip design. ICCAD 2005: 753-758 - [c3]Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang:
Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126 - 2004
- [c2]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen:
Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730 - [c1]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305
Coauthor Index
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