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Letícia Maria Veiras Bolzani
Letícia Maria Veiras Bolzani Poehls – Letícia Maria Bolzani Poehls – Letícia Maria Bolzani Pöhls – Leticia B. Poehls – Leticia Bolzani Poehls
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- affiliation: RWTH Aachen University, Germany
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2020 – today
- 2024
- [j20]Thiago Santos Copetti
, Moritz Fieback
A DfT Strategy for Guaranteeing ReRAM's Quality after Manufacturing. J. Electron. Test. 40(2): 245-257 (2024) - [c78]Moritz Fieback
Lifecycle Management of Emerging Memories. ETS 2024: 1-6 - [c77]Thiago Copetti, A. Chordia, Moritz Fieback
Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs. LATS 2024: 1-6 - [c76]Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Letícia Maria Veiras Bolzani, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. LATS 2024: 1-6 - [c75]Seyed Hossein Hashemi Shadmehri, Supriya Chakraborty, Thiago Santos Copetti, Fabian Luis Vargas, Letícia Maria Bolzani Poehls:
Understanding Transistor Aging Impact on the Behavior of RRAM Cells. VLSI-SoC 2024: 1-6 - [i3]Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Leticia Bolzani Poehls, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. CoRR abs/2403.13655 (2024) - 2023
- [c74]Hanzhi Xun, Moritz Fieback
Characterization and Test of Intermittent Over RESET in RRAMs. ATS 2023: 1-6 - [c73]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. DAC 2023: 1-6 - [c72]Letícia Maria Veiras Bolzani:
Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing? DDECS 2023: 167-168 - [c71]Thiago Santos Copetti, A. Castelnuovo, Tobias Gemmeke, Letícia Maria Veiras Bolzani:
Evaluating a New RRAM Manufacturing Test Strategy. LATS 2023: 1-6 - [c70]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers:
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. LATS 2023: 1-6 - [i2]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR abs/2302.07655 (2023) - 2022
- [c69]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS 2022: 174-177 - [c68]Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE 2022: 957-962 - [c67]Guilherme Cardoso Medeiros, Moritz Fieback
Hierarchical Memory Diagnosis. ETS 2022: 1-2 - [c66]Thiago Santos Copetti, M. Nilovic, Moritz Fieback
Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs. LATS 2022: 1-6 - [i1]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR abs/2204.01501 (2022) - 2021
- [j19]Thiago Copetti
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects. J. Electron. Test. 37(3): 383-394 (2021) - [j18]Letícia Maria Veiras Bolzani
Review of Manufacturing Process Defects and Their Effects on Memristive Devices. J. Electron. Test. 37(4): 427-437 (2021) - [j17]Guilherme Cardoso Medeiros
Hard-to-Detect Fault Analysis in FinFET SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1271-1284 (2021) - [c65]G. Cardoso Medeiros, Moritz Fieback
Improving the Detection of Undefined State Faults in FinFET SRAMs. DTIS 2021: 1-6 - [c64]G. Cardoso Medeiros, Moritz Fieback
Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs. ETS 2021: 1-6 - [c63]E. Brum, Moritz Fieback
Evaluating the Impact of Process Variation on RRAMs. LATS 2021: 1-6 - [c62]Thiago Santos Copetti, Tobias Gemmeke
Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs. VLSI-SoC 2021: 1-6 - [c61]Thiago Santos Copetti, Tobias Gemmeke
A DfT Strategy for Detecting Emerging Faults in RRAMs. VLSI-SoC (Selected Papers) 2021: 93-111 - 2020
- [j16]Thiago Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls:
Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects. J. Electron. Test. 36(2): 271-284 (2020) - [c60]Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Leticia Bolzani Poehls, Tiago R. Balen:
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects. LATS 2020: 1-6
2010 – 2019
- 2019
- [j15]G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen:
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects. J. Electron. Test. 35(2): 191-200 (2019) - [c59]Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback
DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs. ETS 2019: 1-2 - [c58]Thiago Santos Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls:
A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects. LATS 2019: 1-6 - [c57]Estevan Lara, Guilherme Debon, Roger C. Goerl, Paulo Ricardo Cechelero Villa, Dorian Schramm, Leticia B. Poehls, Fabian Vargas:
A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture. LATS 2019: 1-6 - 2018
- [j14]Roger C. Goerl, Paulo Ricardo Cechelero Villa, Letícia Maria Veiras Bolzani, Eduardo Augusto Bezerra, Fabian Luis Vargas:
An efficient EDAC approach for handling multiple bit upsets in memory array. Microelectron. Reliab. 88-90: 214-218 (2018) - [j13]G. Cardoso Medeiros, Letícia Maria Veiras Bolzani, Mottaqiallah Taouil, Fabian Vargas, Said Hamdioui:
A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs. Microelectron. Reliab. 88-90: 355-359 (2018) - [c56]F. Tubiello, Leticia Bolzani Poehls, Thais Webber
A path energy control technique for energy efficiency on wireless sensor networks. LASCAS 2018: 1-4 - [c55]G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen:
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs. LATS 2018: 1-6 - [c54]George Redivo Pinto, Guilherme Cardoso Medeiros, Fabian Vargas, Leticia Bolzani Poehls:
A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects. LATS 2018: 1-6 - 2017
- [c53]Paulo Ricardo Cechelero Villa, Roger C. Goerl, Fabian Vargas, Leticia B. Poehls, Nilberto H. Medina
Analysis of single-event upsets in a Microsemi ProAsic3E FPGA. LATS 2017: 1-4 - [c52]Thiago Santos Copetti, Tiago R. Balen, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls:
Analyzing the behavior of FinFET SRAMs with resistive defects. VLSI-SoC 2017: 1-6 - [c51]Thiago Santos Copetti, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls, Tiago R. Balen:
Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs. VLSI-SoC (Selected Papers) 2017: 22-45 - 2016
- [j12]Maksim Jenihhin
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32(3): 273-289 (2016) - [j11]Thiago Copetti, Guilherme Cardoso Medeiros, Leticia Bolzani Poehls, Fabian Vargas:
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time. J. Electron. Test. 32(3): 315-328 (2016) - [j10]Letícia Maria Bolzani Poehls:
Selected Peer Reviewed Articles from the 17th "IEEE Latin-American Test Symposium, " Foz do Iguaçu, Brazil, April 6-8, 2016. J. Low Power Electron. 12(4): 394 (2016) - [j9]Andres F. Gomez, Felipe Lavratti, Guilherme Medeiros Machado, M. Sartori, Letícia Maria Veiras Bolzani, Víctor H. Champac, Fabian Vargas:
Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. Microelectron. Reliab. 67: 150-158 (2016) - [c50]Adelcio Biazi, César A. M. Marcon
A dynamic TDMA-based sleep scheduling to minimize WSN energy consumption. ICNSC 2016: 1-6 - [c49]Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin
Gate-level modelling of NBTI-induced delays under process variations. LATS 2016: 75-80 - [c48]M. Tulio Martins, G. Cardoso Medeiros, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Poehls:
Analyzing NBTI impact on SRAMs with resistive-open defects. LATS 2016: 87-92 - [c47]G. Cardoso Medeiros, Letícia Maria Bolzani Pöhls, Fabian Vargas:
Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects. VLSID 2016: 487-492 - 2015
- [c46]Sergei Kostin, Jaan Raik
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS 2015: 223-228 - [c45]Christofer de Oliveira, Leticia Bolzani Poehls, Fabian Vargas:
On-chip Watchdog to monitor RTOS activity in MPSoC exposed to noisy environment. EMC Compo 2015: 61-66 - [c44]Marco P. Stefani, Thais Webber
Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs. ISQED 2015: 130-134 - [c43]Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. LATS 2015: 1 - [c42]Thiago Copetti, G. Cardoso Medeiros, Letícia Maria Bolzani Poehls, Fabian Vargas:
NBTI-aware design of integrated circuits: a hardware-based approach. LATS 2015: 1-6 - [c41]N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS 2015: 1-6 - [c40]Ramon Fernandes, Lucas Brahm, Thais Webber
OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip. VLSID 2015: 105-110 - [c39]Felipe Lavratti, Letícia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. VLSID 2015: 405-410 - [c38]Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Víctor H. Champac:
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. VTS 2015: 1-6 - 2014
- [j8]Arthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas, Rubem Dutra Ribeiro Fagundes:
An On-Chip Sensor to Monitor NBTI Effects in SRAMs. J. Electron. Test. 30(2): 159-169 (2014) - [j7]Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera
Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. 30(3): 357-370 (2014) - [j6]Letícia Maria Bolzani Poehls, Matteo Sonza Reorda
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013. J. Low Power Electron. 10(1): 163-164 (2014) - [c37]Sergei Kostin, Jaan Raik
Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW 2014: 1-6 - [c36]César A. M. Marcon
Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization. VLSID 2014: 228-233 - [c35]César A. M. Marcon
Pre-mapping Algorithm for Heterogeneous MPSoCs. VLSID 2014: 252-257 - 2013
- [c34]Raimund Ubar
Identifying NBTI-Critical Paths in Nanoscale Logic. DSD 2013: 136-141 - [c33]C. Oliveira, Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky
Reliability analysis of an on-chip watchdog for embedded systems exposed to radiation and EMI. EMC Compo 2013: 89-94 - [c32]César A. M. Marcon
Phoenix NoC: A distributed fault tolerant architecture. ICCD 2013: 7-12 - [c31]W. Prates, Letícia Maria Veiras Bolzani, Gurgen Harutyunyan, A. Davtyan, Fabian Vargas, Yervant Zorian:
Integrating embedded test infrastructure in SRAM cores to detect aging. IOLTS 2013: 25-30 - [c30]Felipe Lavratti, Letícia Maria Veiras Bolzani, Andrea Calimera
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. LATW 2013: 1-6 - [c29]Sandeep Miryala, Andrea Calimera
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW 2013: 1-6 - [c28]Vinicius Bohrer, Ramon Fernandes, César A. M. Marcon
A flexible framework for modeling and simulation of multipurpose wireless networks. RSP 2013: 94-100 - 2012
- [j5]Marta Portela-García
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. J. Electron. Test. 28(6): 777-789 (2012) - [j4]Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky
A Test Platform for Dependability Analysis of SoCs Exposed to EMI and Radiation. J. Electron. Test. 28(6): 803-816 (2012) - [c27]Arthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas:
On-chip aging sensor to monitor NBTI effect in nano-scale SRAM. DDECS 2012: 354-359 - [c26]Arthur Ceratti, Thiago Copetti, Letícia Maria Veiras Bolzani, Fabian Vargas:
Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM. LATW 2012: 1-6 - 2011
- [j3]Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. 7(4): 529-530 (2011) - [c25]Dhiego Silva, Kleber Stangherlin, Letícia Maria Veiras Bolzani, Fabian Vargas:
A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems. ETS 2011: 209 - [c24]Dhiego Silva, Letícia Maria Veiras Bolzani, Fabian Vargas:
An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems. IOLTS 2011: 19-24 - [c23]Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky
Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity. LATW 2011: 1-6 - [c22]Felipe Lavratti, Andrea Calimera
A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs. LATW 2011: 1-6 - [c21]Marta Portela-García
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study. LATW 2011: 1-6 - 2010
- [j2]Paolo Bernardi
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs. IEEE Trans. Dependable Secur. Comput. 7(4): 439-445 (2010) - [c20]Felipe Lavratti, Alex R. Pinto
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. DSD 2010: 509-515 - [c19]Raul Chipana, Letícia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião
Investigating the Use of BICS to detect resistive-open defects in SRAMs. IOLTS 2010: 200-201 - [c18]Raul Chipana, Letícia Maria Veiras Bolzani, Fabian Vargas:
BICS-based March test for resistive-open defect detection in SRAMs. LATW 2010: 1-6 - [c17]Felipe Lavratti, Alex R. Pinto
Towards a transmission power self-optimization in reliable Wireless Sensor Networks. LATW 2010: 1-3
2000 – 2009
- 2009
- [c16]Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339 - [c15]Jimmy Tarrillo
A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems. DSD 2009: 341-347 - [c14]Letícia Maria Veiras Bolzani, Andrea Calimera
Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS 2009: 1723-1726 - 2008
- [c13]Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303 - 2007
- [c12]Letícia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero:
Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores. IEEE Congress on Evolutionary Computation 2007: 3474-3481 - [c11]Paolo Bernardi
Extended Fault Detection Techniques for Systems-on-Chip. DDECS 2007: 55-60 - [c10]Letícia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero
Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores. GECCO 2007: 1912-1919 - [c9]Paolo Bernardi
A Hybrid Approach to Fault Detection and Correction in SoCs. IOLTS 2007: 107-112 - [c8]Letícia Maria Veiras Bolzani, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. IOLTS 2007: 265-270 - [c7]Letícia Maria Veiras Bolzani, Paolo Bernardi
An optimized hybrid approach to provide fault detection and correction in SoCs. SBCCI 2007: 342-347 - [c6]Letícia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda
A software-based methodology for the generation of peripheral test sets based on high-level descriptions. SBCCI 2007: 348-353 - 2006
- [j1]Paolo Bernardi
A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006) - [c5]Paolo Bernardi
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV 2006: 3-8 - 2005
- [c4]Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453 - [c3]Paolo Bernardi
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58 - 2004
- [c2]Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante:
Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88 - 2003
- [c1]Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Letícia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? IOLTS 2003: 163
Coauthor Index
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