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David Meisner
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2020 – today
- 2024
- [c17]Mike Chow, Yang Wang, William Wang, Ayichew Hailu, Rohan Bopardikar, Bin Zhang, Jialiang Qu, David Meisner, Santosh Sonawane, Yunqi Zhang, Rodrigo Paim, Mack Ward, Ivor Huang, Matt McNally, Daniel Hodges, Zoltan Farkas, Caner Gocmen, Elvis Huang, Chunqiang Tang:
ServiceLab: Preventing Tiny Performance Regressions at Hyperscale through Pre-Production Testing. OSDI 2024: 545-562
2010 – 2019
- 2017
- [j3]Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas F. Wenisch, Ronald G. Dreslinski, Jason Mars, Lingjia Tang:
Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline. ACM Trans. Comput. Syst. 35(1): 2:1-2:33 (2017) - 2016
- [c16]Yunqi Zhang, David Meisner, Jason Mars, Lingjia Tang:
Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference. ISCA 2016: 456-468 - 2015
- [c15]Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas F. Wenisch, Jason Mars, Lingjia Tang, Ronald G. Dreslinski:
Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. HPCA 2015: 271-282 - 2014
- [c14]Michael Chow, David Meisner, Jason Flinn, Daniel Peek, Thomas F. Wenisch:
The Mystery Machine: End-to-end Performance Analysis of Large-scale Internet Services. OSDI 2014: 217-231 - 2013
- [c13]Kevin T. Lim, David Meisner, Ali G. Saidi, Parthasarathy Ranganathan, Thomas F. Wenisch:
Thin servers with smart pipes: designing SoC accelerators for memcached. ISCA 2013: 36-47 - 2012
- [b1]David Meisner:
Architecting Efficient Data Centers. University of Michigan, USA, 2012 - [j2]Qingyuan Deng, Luiz E. Ramos, Ricardo Bianchini, David Meisner, Thomas F. Wenisch:
Active Low-Power Modes for Main Memory with MemScale. IEEE Micro 32(3): 60-69 (2012) - [c12]David Meisner, Thomas F. Wenisch:
DreamWeaver: architectural support for deep sleep. ASPLOS 2012: 313-324 - [c11]Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini:
MultiScale: memory system DVFS with multiple memory controllers. ISLPED 2012: 297-302 - [c10]David Meisner, Junjie Wu, Thomas F. Wenisch:
BigHouse: A simulation infrastructure for data center systems. ISPASS 2012: 35-45 - [c9]Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini:
CoScale: Coordinating CPU and Memory System DVFS in Server Systems. MICRO 2012: 143-154 - 2011
- [j1]David Meisner, Brian T. Gold, Thomas F. Wenisch:
The PowerNap Server Architecture. ACM Trans. Comput. Syst. 29(1): 3:1-3:24 (2011) - [c8]Qingyuan Deng, David Meisner, Luiz E. Ramos, Thomas F. Wenisch, Ricardo Bianchini:
MemScale: active low-power modes for main memory. ASPLOS 2011: 225-238 - [c7]David Meisner, Christopher M. Sadler, Luiz André Barroso, Wolf-Dietrich Weber, Thomas F. Wenisch:
Power management of online data-intensive services. ISCA 2011: 319-330 - [c6]David Meisner, Thomas F. Wenisch:
Does low-power design imply energy efficiency for data centers? ISLPED 2011: 109-114 - [c5]David Meisner, Junjie Wu, Thomas F. Wenisch:
Towards a scalable data center-level evaluation methodology. ISPASS 2011: 121-122 - 2010
- [c4]Steven Pelley, David Meisner, Pooya Zandevakili, Thomas F. Wenisch, Jack Underwood:
Power routing: dynamic power provisioning in the data center. ASPLOS 2010: 231-242 - [c3]David Meisner, Thomas F. Wenisch:
Peak power modeling for data center servers with switched-mode power supplies. ISLPED 2010: 319-324
2000 – 2009
- 2009
- [c2]David Meisner, Brian T. Gold, Thomas F. Wenisch:
PowerNap: eliminating server idle power. ASPLOS 2009: 205-216 - 2007
- [c1]David Meisner, Sherief Reda:
Hardware libraries: An architecture for economic acceleration in soft multi-core environments. ICCD 2007: 179-186
Coauthor Index
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