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Article

CoScale: Coordinating CPU and Memory System DVFS in Server Systems

Authors:

Abhishek Bhattacharjee,

Thomas F. Wenisch,

Ricardo BianchiniAuthors Info & Claims

MICRO-45: Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

Pages 143 - 154

https://doi.org/10.1109/MICRO.2012.22

Published: 01 December 2012 Publication History

Abstract

Recent work has introduced memory system dynamic voltage and frequency scaling (DVFS), and has suggested that balanced scaling of both CPU and the memory system is the most promising approach for conserving energy in server systems. In this paper, we first demonstrate that CPU and memory system DVFS often conflict when performed independently by separate controllers. In response, we propose Co Scale, the first method for effectively coordinating these mechanisms under performance constraints. Co Scale relies on execution profiling of each core via (existing and new) performance counters, and models of core and memory performance and power consumption. Co Scale explores the set of possible frequency settings in such a way that it efficiently minimizes the full-system energy consumption within the performance bound. Our results demonstrate that, by effectively coordinating CPU and memory power management, Co Scale conserves a significant amount of system energy compared to existing approaches, while consistently remaining within the prescribed performance bounds. The results also show that Co Scale conserves almost as much system energy as an offline, idealized approach.

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Cited By

Esper KWildermann STeich J(2023)Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary AlgorithmsACM Transactions on Design Automation of Electronic Systems10.1145/361783228:6(1-20)Online publication date: 16-Oct-2023
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Srivastava TZhang HHoffmann H(2022)Penelope: Peer-to-peer Power ManagementProceedings of the 51st International Conference on Parallel Processing10.1145/3545008.3545047(1-11)Online publication date: 29-Aug-2022
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Muralidhar RBorovica-Gajic RBuyya R(2022)Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and StandardsACM Computing Surveys10.1145/351109454:11s(1-37)Online publication date: 9-Sep-2022
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CoScale: Coordinating CPU and Memory System DVFS in Server Systems

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cover image ACM Conferences

MICRO-45: Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

December 2012

487 pages

ISBN:9780769549248

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS: Computer Society

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 2012

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

Esper KWildermann STeich J(2023)Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary AlgorithmsACM Transactions on Design Automation of Electronic Systems10.1145/361783228:6(1-20)Online publication date: 16-Oct-2023
https://dl.acm.org/doi/10.1145/3617832
Srivastava TZhang HHoffmann H(2022)Penelope: Peer-to-peer Power ManagementProceedings of the 51st International Conference on Parallel Processing10.1145/3545008.3545047(1-11)Online publication date: 29-Aug-2022
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Muralidhar RBorovica-Gajic RBuyya R(2022)Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and StandardsACM Computing Surveys10.1145/351109454:11s(1-37)Online publication date: 9-Sep-2022
https://dl.acm.org/doi/10.1145/3511094
Zhang DPanwar GKotra JDeBardeleben NBlanchard SJian XMartínez JDuato JJohn L(2021)Quantifying server memory frequency margin and using it to improve performance in HPC systemsProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00064(748-761)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00064
Asyabi EBestavros ASharafzadeh EZhu TFonseca RDelimitrou COoi B(2020)PeafowlProceedings of the 11th ACM Symposium on Cloud Computing10.1145/3419111.3421298(150-164)Online publication date: 12-Oct-2020
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Owahid AJohn E(2019)Wasted dynamic power and correlation to instruction set architecture for CPU throttlingThe Journal of Supercomputing10.1007/s11227-018-2637-675:5(2436-2454)Online publication date: 1-May-2019
https://dl.acm.org/doi/10.1007/s11227-018-2637-6
Rahmani ADonyanavard BMück TMoazzemi KJantsch AMutlu ODutt N(2018)SPECTRACM SIGPLAN Notices10.1145/3296957.317319953:2(169-183)Online publication date: 19-Mar-2018
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Hsu CDeng QMars JTang L(2018)SmoothOperatorACM SIGPLAN Notices10.1145/3296957.317319053:2(535-548)Online publication date: 19-Mar-2018
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Rahmani ADonyanavard BMück TMoazzemi KJantsch AMutlu ODutt NShen XTuck JBianchini RSarkar V(2018)SPECTRProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173199(169-183)Online publication date: 19-Mar-2018
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Hsu CDeng QMars JTang LShen XTuck JBianchini RSarkar V(2018)SmoothOperatorProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173190(535-548)Online publication date: 19-Mar-2018
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