[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/1950365.1950392acmconferencesArticle/Chapter ViewAbstractPublication PagesasplosConference Proceedingsconference-collections
research-article

MemScale: active low-power modes for main memory

Published: 05 March 2011 Publication History

Abstract

Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. However, these states require entire DRAM ranks to be idled, which is difficult to achieve even in lightly loaded servers. In this paper, we propose to conserve memory energy while improving its energy-proportionality by creating active low-power modes for it. Specifically, we propose MemScale, a scheme wherein we apply dynamic voltage and frequency scaling (DVFS) to the memory controller and dynamic frequency scaling (DFS) to the memory channels and DRAM devices. MemScale is guided by an operating system policy that determines the DVFS/DFS mode of the memory subsystem based on the current need for memory bandwidth, the potential energy savings, and the performance degradation that applications are willing to withstand. Our results demonstrate that MemScale reduces energy consumption significantly compared to modern memory energy management approaches. We conclude that the potential benefits of the MemScale mechanisms and policy more than compensate for their small hardware cost.

References

[1]
J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future scaling of processor-memory interfaces. SC '09 - Super Computing, 2009.
[2]
I. Akyildiz. On the exact and approximate throughput analysis of closed queuing networks with blocking. IEEE Transactions on Software Engineering, 14(1):62--70, 1988.
[3]
AMD. ACP -- The Truth About Power Consumption Starts Here, 2009. http://www.amd.com/us/Documents/43761C_ACP_WP_EE.pdf.
[4]
S. Balsamo, V. D. N. Persone, and R. Onvural. Analysis of Queuing Networks with Blocking. 2001.
[5]
L. A. Barroso and U. Hölzle. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines. Synthesis Lectures on Computer Architecture, Jan. 2009.
[6]
L. A. Barroso and U. Hölzle. The Case for Energy-Proportional Computing. IEEE Computer, 40(12):33--37, December 2007.
[7]
N. Binkert, R. Dreslinski, L. Hsu, K. Lim, a.G. Saidi, and S. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4):52--60, July 2006.
[8]
R. Crisp. Direct Rambus Technology: The New Main Memory Standard. IEEE Micro, 1997.
[9]
R. Das, O. Mutlu, T. Moscibroda, and C. R. Das. Aérgia : Exploiting Packet Latency Slack in On-Chip Networks. ISCA '10: International Symposium on Computer Architecture, 2010.
[10]
V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Transactions on Computers, 50(11), 2001.
[11]
B. Diniz, D. Guedes, W. M. Jr, and R. Bianchini. Limiting the Power Consumption of Main Memory. ISCA '07: International Symposium on Computer Architecture, 2007.
[12]
EPA. Report to Congress on Server and Data Center Energy Efficiency Public Law 109--431, 2007.
[13]
X. Fan, C. Ellis, and A. Lebeck. Memory Controller Policies for DRAM Power Management. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.
[14]
W. Felter, K. Rajamani, T. Keller, and C. Rusu. A Performance-Conserving Approach for Reducing Peak Power Consumption in Server Systems. ICS '05: International Conference on Supercomputing, 2005.
[15]
Google. Going Green at Google, 2010.
[16]
E. Gorbatov, 2010. Personal communication.
[17]
M. S. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. HPCA '08: High Performance Computer Architecture, 2008.
[18]
H. Hanson and K. Rajamani. What Computer Architects Need to Know About Memory Throttling. WEED '10: Workshop on Energy-Efficient Design, 2010.
[19]
S. Herbert and D. Marculescu. Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors. ISLPED '07: International Symposium on Low Power Electronics and Design, 2007.
[20]
H. Huang, P. Pillai, and K. G. Shin. Design and Implementation of Power-Aware Virtual Memory. In Proceedings of the USENIX Annual Technical Conference, June 2003.
[21]
Intel. Intel Xeon Processor 5600 Series, 2010.
[22]
B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers, 2007.
[23]
JEDEC. DDR3 SDRAM Standard, 2009.
[24]
A. R. Lebeck, X. Fan, H. Zeng, and C. Ellis. Power Aware Page Allocation. ASPLOS '00: Architectural Support for Programming Languages and Operating Systems, 2000.
[25]
C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller. Energy Management for Commercial Servers. IEEE Computer, 36(12), December 2003.
[26]
D. Levinthal. Performance Analysis Guide for Intel Core i7 Processor and Intel Xeon 5500 processors, 2009.
[27]
X. Li, Z. Li, F. M. David, P. Zhou, Y. Zhou, S. V. Adve, and S. Kumar. Performance-directed energy management for main memory and disks. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, October 2004.
[28]
K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. K. Reinhardt, and T. F. Wenisch. Disaggregated Memory for Expansion and Sharing in Blade Servers. ISCA '09: International Symposium on Computer Architecture, 2009.
[29]
J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Thermal Modeling and Management of DRAM Memory Systems. ISCA '07: International Symposium on Computer Architecture, 2007.
[30]
J. Lin, H. Zheng, Z. Zhu, E. Gorbatov, H. David, and Z. Zhang. Software Thermal Management of DRAM Memory for Multicore Systems. SIGMETRICS, pages 337--348, 2008.
[31]
D. Meisner, B. T. Gold, and T. F. Wenisch. PowerNap: Eliminating Server Idle Power. ASPLOS '09: Architectural Support for Programming Languages and Operating Systems, Feb. 2009.
[32]
Micron. 1Gb: x4, x8, x16 DDR3 SDRAM, 2006.
[33]
Micron. Calculating Memory System Power for DDR3, July 2007.
[34]
A. Miyoshi, C. Lefurgy, E. V. Hensbergen, R. Rajamony, and R. Rajkumar. Critical Power Slope : Understanding the Runtime Effects of Frequency Scaling. ICS '02: International Conference on Supercomputing, 2002.
[35]
J. Moore, J. S. Chase, and P. Ranganathan. Weatherman: Automated, Online and Predictive Thermal Mapping and Management for Data Centers. ICAC '06: International Conference on Autonomic Computing, 2006.
[36]
V. Pandey, W. Jiang, Y. Zhou, and R. Bianchini. DMA-Aware Memory Energy Management. HPCA '06: High-Performance Computer Architecture, 2006.
[37]
S. Pelley, D. Meisner, P. Zandevakili, T. F. Wenisch, and J. Underwood. Power Routing : Dynamic Power Provisioning in the Data Center. ASPLOS '10: Architectural Support for Programming Languages and Operating Systems, 2010.
[38]
E. Perelman, G. Hamerly, M. V. Biesbrouck, T. Sherwood, and B. Calder. Using SimPoint for Accurate and Efficient Simulation Erez Perelman. SIGMETRICS, 2003.
[39]
L. Ramos and R. Bianchini. C-Oracle: Predictive thermal management for data centers. HPCA '08: High Performance Computer Architecture, Feb. 2008.
[40]
K. Sudan, N. Chatterjee, D. Nellans, M. Awasthi, Rajeev Balasubramonian, and A. Davis. Micro-Pages : Increasing DRAM Efficiency with Locality-Aware Data Placement. ASPLOS '10: Architectural Support for Programming Languages and Operating Systems, 2010.
[41]
N. Tolia, Z. Wang, M. Marwah, C. Bash, P. Ranganathan, and X. Zhu. Delivering Energy Proportionality with Non Energy-Proportional Systems â Optimizing the Ensemble. HotPower, 2008.
[42]
D. Tsirogiannis, S. Harizopoulos, and M. A. Shah. Analyzing the energy efficiency of a database server. SIGMOD, 2010.
[43]
A. N. Udipi, N. Muralimanohar, N. Chatterjee, Rajeev Balasubramonian, A. Davis, and N. P. Jouppi. Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores. ISCA '10: International Symposium on Computer Architecture, 2010.
[44]
H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO '08: Symposium on Microarchitecture, Nov. 2008.
[45]
H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. Decoupled DIMM : Building High-Bandwidth Memory System Using Low-Speed DRAM Devices. ISCA '09: International Symposium on Computer Architecture, 2009.

Cited By

View all
  • (2024)SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00036(325-336)Online publication date: 27-May-2024
  • (2023)JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy EfficiencyProceedings of the 52nd International Conference on Parallel Processing10.1145/3605573.3605586(828-838)Online publication date: 7-Aug-2023
  • (2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
  • Show More Cited By

Index Terms

  1. MemScale: active low-power modes for main memory

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
    March 2011
    432 pages
    ISBN:9781450302661
    DOI:10.1145/1950365
    • cover image ACM SIGARCH Computer Architecture News
      ACM SIGARCH Computer Architecture News  Volume 39, Issue 1
      ASPLOS '11
      March 2011
      407 pages
      ISSN:0163-5964
      DOI:10.1145/1961295
      Issue’s Table of Contents
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 46, Issue 3
      ASPLOS '11
      March 2011
      407 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1961296
      Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 05 March 2011

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. dynamic voltage and frequency scaling
    2. energy conservation
    3. memory subsystem

    Qualifiers

    • Research-article

    Conference

    ASPLOS'11

    Acceptance Rates

    Overall Acceptance Rate 535 of 2,713 submissions, 20%

    Upcoming Conference

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)27
    • Downloads (Last 6 weeks)6
    Reflects downloads up to 11 Dec 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS57955.2024.00036(325-336)Online publication date: 27-May-2024
    • (2023)JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy EfficiencyProceedings of the 52nd International Conference on Parallel Processing10.1145/3605573.3605586(828-838)Online publication date: 7-Aug-2023
    • (2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
    • (2022)Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and StandardsACM Computing Surveys10.1145/351109454:11s(1-37)Online publication date: 9-Sep-2022
    • (2022)Graphics Peeping Unit: Exploiting EM Side-Channel Information of GPUs to Eavesdrop on Your Neighbors2022 IEEE Symposium on Security and Privacy (SP)10.1109/SP46214.2022.9833773(1440-1457)Online publication date: May-2022
    • (2022)AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter ServersProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00065(851-867)Online publication date: 1-Oct-2022
    • (2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server ApplicationsProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00063(835-850)Online publication date: 1-Oct-2022
    • (2022)Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN53405.2022.00054(475-487)Online publication date: Jun-2022
    • (2022)Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory SystemIEEE Access10.1109/ACCESS.2022.317410110(52565-52608)Online publication date: 2022
    • (2022)A Modern Primer on Processing in MemoryEmerging Computing: From Devices to Systems10.1007/978-981-16-7487-7_7(171-243)Online publication date: 9-Jul-2022
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media